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PDF ICS85310I-31 Data sheet ( Hoja de datos )

Número de pieza ICS85310I-31
Descripción DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
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No Preview Available ! ICS85310I-31 Hoja de datos, Descripción, Manual

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Integrated
Circuit
Systems, Inc.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85310I-31 is a low skew, high performance • 2 differential 2.5V/3.3V LVPECL / ECL bank outputs
ICS dual 1-to-5 Differential-to-2.5V/3.3V ECL/LVPECL
HiPerClockS™ Fanout Buffer and a member of the HiPerClockS™ • 2 differential clock input pairs
family of High Performance Clock Solutions from • CLKx, nCLKx pairs can accept the following differential
ICS. The CLKx, nCLKx pairs can accept most input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
standard differential input levels. The ICS85310I-31 is charac-
terized to operate from either a 2.5V or a 3.3V power supply. • Maximum output frequency: 700MHz
Guaranteed output and part-to-part skew characteristics make • Translates any single ended input signal to 3.3V
the ICS85310I-31 ideal for those clock distribution applications LVPECL levels with resistor bias on nCLKx input
demanding well defined performance and repeatability.
• Output skew: 25ps (typical)
• Part-to-part skew: 270ps (typical)
• Propagation delay: 1.7ns (typical)
Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range:
V = 2.375V to 3.8V, V = 0V
CC EE
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLKA
nCLKA
CLK_ENA
D
Q
LE
CLKB
nCLKB
CLK_ENB
D
Q
LE
85310AYI-31
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
PIN ASSIGNMENT
VCC
CLK_ENA
CLKA
nCLKA
CLK_ENB
CLKB
nCLKB
VEE
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS85310I-31 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
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1
REV. D JULY 6, 2005

1 page




ICS85310I-31 pdf
Integrated
Circuit
Systems, Inc.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum
VCCO - 1.0
VCCO - 1.7
1.0
Units
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
ƒ500MHz
700
1.7 2.2
25 50
tsk(pp) Part-to-Part Skew; NOTE 3, 4
270 550
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
<0.13
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
20% to 80%
20% to 80%
200
200
47
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
700
700
53
Units
MHz
ns
ps
ps
ps
ps
ps
%
85310AYI-31
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REV. D JULY 6, 2005

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ICS85310I-31 arduino
Integrated
Circuit
Systems, Inc.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310I-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW
Power (outputs) = 30.94mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power (3.8V, with all outputs switching) = 456mW + 309.4mW = 765.4mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.765W * 42.1°C/W = 117.2°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
85310AYI-31
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