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PDF ICS85310I-11 Data sheet ( Hoja de datos )
| Número de pieza | ICS85310I-11 | |
| Descripción | ECL/LVPECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85310I-11 is a low skew, high perfor-
ICS mance 1-to-10 Differential-to-2.5V/3.3V ECL/
HiPerClockS™ LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Perfor mance
Clock Solutions from ICS. The CLKx, nCLKx
pairs can accept most standard differential input levels. The
ICS85310I-11 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85310I-11 ideal
for those clock distribution applications demanding well de-
fined performance and repeatability.
FEATURES
• 10 differential 2.5V/3.3V LVPECL / ECL outputs
• 2 selectable differential input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (typical)
• Part-to-part skew: 140ps (typical)
• Propagation delay: 2ns (typical)
• Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS complaint
BLOCK DIAGRAM
CLK0
nCLK0
CLK1
nCLK1
0
1
CLK_SEL
CLK_EN
D
Q
LE
85310AYI-11
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
32 31 30 29 28 27 26 25
Q2
nQ2
VCC
CLK_SEL
1
2
24 Q3
23 nQ3
Q3 CLK0 3
22 Q4
nQ3
Q4
nCLK0
CLK_EN
4
5
ICS85310I-11 21 nQ4
20 Q5
nQ4
CLK1 6
19 nQ5
Q5
nQ5
nCLK1
VEE
7
8
18 Q6
17 nQ6
Q6
nQ6
9 10 11 12 13 14 15 16
Q7
nQ7
32-Lead LQFP
Q8 7mm x 7mm x 1.4mm package body
nQ8 Y Package
Q9 Top View
nQ9
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1
REV. E JULY 7, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
VCC - 1.4
VCC - 2.0
0.6
Maximum
VCC - 1.0
VCC - 1.7
0.85
Units
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
t
PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 500MHz
700
2 2.5
30 55
tsk(pp) Part-to-Part Skew; NOTE 3, 4
140 340
Buffer Additive Phase Jitter,
tjit RMS; refer to Additive Phase
Jitter Section
<0.13
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
20% to 80%
20% to 80%
200
200
47
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
700
700
53
Units
MHz
ns
ps
ps
ps
ps
ps
%
85310AYI-11
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5
REV. E JULY 7, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW
• Power (outputs) = 30.2mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power (3.8V, with all outputs switching) = 456mW + 302mW = 758mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.758W * 42.1°C/W = 117°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
85310AYI-11
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| PDF Descargar | [ Datasheet ICS85310I-11.PDF ] | |
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