PDF ICS8531-01 Data sheet ( Hoja de datos )

Número de pieza	ICS8531-01
Descripción	LVPECL FANOUT BUFFER
Fabricantes	ICST
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS8531-01 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION The ICS8531-01 is a low skew, high performance ,&6 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer HiPerClockS™ a n d a m e m b e r o f t h e H i P e r C l o c k S ™ family of High Performance Clock Solutions from ICS. The ICS8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the out- puts during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew characteris- tics make the ICS8531-01 ideal for high performance work- station and server applications. FEATURES • 9 differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 500MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 2ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM CLK_EN CLK nCLK PCLK nPCLK CLK_SEL 0 1 D Q LE PIN ASSIGNMENT 32 31 30 29 28 27 26 25 Q0 nQ0 VCC CLK 1 2 2 4 VCCO 23 Q3 Q1 nCLK 3 22 nQ3 nQ1 CLK_SEL 4 ICS8531-01 21 Q4 Q2 PCLK 5 20 nQ4 nQ2 nPCLK 6 19 Q5 Q3 nQ3 VEE CLK_EN 7 8 18 nQ5 1 7 VCCO Q4 nQ4 9 10 11 12 13 14 15 16 Q5 nQ5 32-Lead LQFP Q6 7mm x 7mm x 1.4mm package body nQ6 Y package Q7 Top View nQ7 Q8 nQ8 8531AY-01 www.icst.com/products/hiperclocks.html 1 REV. B AUGUST 9, 2001 1 page Integrated Circuit Systems, Inc. ICS8531-01 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical IIH IIL VPP VCMR PCLK Input High Current nPCLK PCLK Input Low Current nPCLK Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 VCC = VIN = 3.465V V = V = 3.465V CC IN VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.3 VEE + 1.5 VOH Output High Voltage; NOTE 3 VCCO - 1.4 VOL Output Low Voltage; NOTE 3 VCCO - 2.0 VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCCO - 2V. Maximum 150 5 1 VCC VCCO - 1.0 VCCO - 1.7 0.85 Units µA µA µA µA V V V V V TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum fMAX tPD tsk(o) Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 ƒ≤ 250MHz 1 500 2 50 tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 tR Output Rise Time tF Output Fall Time odc Output Duty Cycle 20% to 80% @ 50MHz 300 700 20% to 80% @ 50MHz 300 700 48 50 52 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Units MHz ns ps ps ps ps % 8531AY-01 www.icst.com/products/hiperclocks.html 5 REV. B AUGUST 9, 2001 5 Page Integrated Circuit Systems, Inc. ICS8531-01 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE q by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs. TRANSISTOR COUNT The transistor count for ICS8531-01 is: 632 8531AY-01 www.icst.com/products/hiperclocks.html 11 REV. B AUGUST 9, 2001 11 Page

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