DataSheet.es    


PDF ICS8530I-01 Data sheet ( Hoja de datos )

Número de pieza ICS8530I-01
Descripción LVPECL FANOUT BUFFER
Fabricantes ICST 
Logotipo ICST Logotipo



Hay una vista previa y un enlace de descarga de ICS8530I-01 (archivo pdf) en la parte inferior de esta página.


Total 17 Páginas

No Preview Available ! ICS8530I-01 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8530I-01 is a low skew, 1-to-16 Differ-
ential-to-3.3V LVPECL Fanout Buffer and a mem-
HiPerClockS™ ber of the HiPerClockS™family of High Perfor-
mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
levels. The high gain differential amplifier accepts peak-to-
peak input voltages as small as 150mV as long as the com-
mon mode voltage is within the specified minimum and maxi-
mum range.
Guaranteed output and part-to-part skew characteristics make
the ICS8530I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
(16) differential 3.3V LVPECL outputs
CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 500MHz
Translates any single-ended input signal to
3.3V LVPECL levels with a resistor bias on nCLK input
Output skew: 50ps (typical)
Part-to-part skew: 100ps (typical)
Additive phase jitter, RMS @ 106.25MHz:
0.022ps (typical) @ 25°C
3.3V output operating supply
-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q15
nQ15
Q14
nQ14
VCCO
Q11
nQ11
Q10
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
CLK
VCCO
nQ0
Q0
Q2
Q13 nQ10 5
32 nQ1
nQ2
Q3
nQ13
Q12
VEE 6
Q9 7
ICS8530I-01
31 Q1
3 0 VEE
nQ3
nQ12
nQ9 8
29 nQ2
Q4
nQ4
Q5
nQ5
Q11
nQ11
Q10
nQ10
Q8
nQ8
VCCO
VCC
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
Q2
nQ3
Q3
Vcco
Q6
nQ6
Q9
nQ9
Q7 Q8
nQ7
nQ8
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm body package
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8530DYI-01
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 25, 2005

1 page




ICS8530I-01 pdf
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter @
106.25MHz, 25°C (12KHz to 20MHz)
= 0.022ps typical
10k
100k
1M
10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
8530DYI-01
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 25, 2005

5 Page





ICS8530I-01 arduino
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8530I-01
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3 R4
125 125
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
84 84
3.3V
LVDS_Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
LVPECL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R3 R4
125 125
C1
C2
R5
100 - 200
R6
100 - 200
R1 R2
84 84
3.3V
CLK
nCLK HiPerClockS
Input
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
8530DYI-01
www.icst.com/products/hiperclocks.html
11
REV. A FEBRUARY 25, 2005

11 Page







PáginasTotal 17 Páginas
PDF Descargar[ Datasheet ICS8530I-01.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS8530I-01LVPECL FANOUT BUFFERICST
ICST
ICS8530I-011-To-16 Differentail-To-3.3V LVPECL Fanout BufferIntegrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar