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PDF ICS853054 Data sheet ( Hoja de datos )

Número de pieza ICS853054
Descripción LVPECL/ECL CLOCK MULTIPLEXER
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
GENERAL DESCRIPTION
The ICS853054 is an 4:1 Differential-to-3.3V or
ICS 2.5V LVPECL/ECL Clock Multiplexer which
HiPerClockS™ can operate up to 2.5GHz and is a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853054 has 4
selectable differential clock inputs. The PCLKx, nPCLKx in-
put pairs can accept LVPECL, LVDS, CML or SSTL levels.
The fully differential architecture and low propagation
delay make it ideal for use in clock distribution circuits. The
select pins have internal pulldown resistors. The SEL1 pin is
the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00
selects PCLK0, nPCLK0).
FEATURES
High speed 4:1 differential multiplexer
One differential 3.3V or 2.5V LVPECL output
Four selectable differential PCLK, nPCLK inputs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 3.2GHz
Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
Part-to-part skew: TBD
Propagation delay: 465ps (typical)
Additive phase jitter, RMS: 0.238ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
ECL mode operating voltage supply range:
V = 0V, V = -3.465V to -2.375V
CC EE
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
00
01
10
11
SEL1 SEL0
Q
nQ
PIN ASSIGNMENT
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
VEE
1
2
3
4
5
6
7
8
16 VCC
15 Q
14 nQ
13 VEE
12 nPCLK3
11 PCLK3
10 nPCLK2
9 PCLK2
ICS853054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853054AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
1

1 page




ICS853054 pdf
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter, RMS
@ 155.52MHz = <0.238ps typical
10k 100k 1M 10M
OFFSET FROM CARRIER FREQUENCY (HZ)
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853054AG
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REV. A JANUARY 5, 2006

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ICS853054 arduino
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853054.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853054 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V ± 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 61mA = 211.37mW
Power (outputs)MAX = 27.83mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 211.37mW + 27.83mW = 239.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 meters per second and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.239W * 81.8°C/W = 104.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP FORCED CONVECTION
θJA by Velocity (Meters per Second)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853054AG
www.icst.com/products/hiperclocks.html
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