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PDF ICS853031 Data sheet ( Hoja de datos )
| Número de pieza | ICS853031 | |
| Descripción | LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS853031 is a low skew, high performance
1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL
Fanout Buffer and a member of the HiPerClockS™
• 9 differential 2.5V/3.3V LVPECL/ECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
family of High Performance Clock Solutions from • CLK, nCLK pair can accept the following differential
ICS. The ICS853031 has two selectable clock in- input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL,
puts. The CLK, nCLK pair can accept most standard differential
input levels.The PCLK, nPCLK pair can accept LVPECL, LVDS,
CML, or SSTL input levels. The clock enable is internally syn-
• PCLK, nPCLK supports the following input types:
LVPECL, LVDS, CML, SSTL
chronized to eliminate runt pulses on the outputs during asyn- • Output frequency: 1.6GHz (typical)
chronous assertion/deassertion of the clock enable pin.
• Translates any single ended input signal (LVCMOS, LVTTL,
Guaranteed output skew and part-to-part skew characteristics GTL) to 3.3V LVPECL levels with resistor bias on nCLK or
make the ICS853031 ideal for high performance workstation nPCLK inputs
and server applications.
• Output skew: 20ps (typical)
• Part-to-part skew: 75ps (typical)
• Propagation delay: 875ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
V = 0V, V = -2.375V to -3.465V
CC EE
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin compatible with ICS8531-01
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
0
1
D
Q
LE
32 31 30 29 28 27 26 25
Q0
nQ0
VCC
CLK
1
2
2 4 VCCO
23 Q3
Q1 nCLK 3
22 nQ3
nQ1
CLK_SEL
PCLK
4
5
ICS853031
21 Q4
20 nQ4
Q2
nQ2
nPCLK 6
19 Q5
Q3
nQ3
VEE
CLK_EN
7 18
8 17
9 10 11 12 13 14 15 16
nQ5
VCCO
Q4
nQ4
Q5
nQ5 32-Lead LQFP
Q6 7mm x 7mm x 1.4mm package body
nQ6 Y package
Top View
Q7
nQ7
Q8
nQ8
853031AY
www.icst.com/products/hiperclocks.html
1
REV. B SEPTEMBER 16, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 3.3V; VEE = 0V
Symbol Parameter
-40°C
25°C
Min Typ Max Min Typ Max Min
VOH
VOL
VPP
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
2.175 2.275 2.38 2.225 2.295 2.37
1.405 1.545 1.68 1.425 1.52 1.615
0.15 0.8 1.3 0.15 0.8 1.3
1.2 VCC 1.2
VCC
2.22
1.44
0.15
1.2
PCLK
IIH
Input High Current
nPCLK
150 150
10 10
PCLK
-50
IIL
Input Low Current
nPCLK
-150
-50
-150
-50
-150
Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.165V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
85°C
Typ
2.295
1.535
0.8
Max
2.365
1.63
1.3
VCC
150
10
Units
V
V
V
V
µA
µA
µA
µA
TABLE 4E. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 2.5V; VEE = 0V
Symbol Parameter
-40°C
25°C
Min Typ Max Min Typ Max Min
V
OH
VOL
VPP
V
CMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
1.375 1.475 1.58 1.425 1.495 1.57
0.605 0.745 0.88 0.625 0.72 0.815
0.15 0.8 1.3 0.15 0.8 1.3
1.2 V 1.2
CC
V
CC
1.42
0.64
0.15
1.2
PCLK
IIH
Input High Current
nPCLK
150 150
10 10
PCLK
-10
IIL
Input Low Current
nPCLK
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.125V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
85°C
Typ
1.495
0.735
0.8
Max
1.565
0.83
1.3
V
CC
150
10
Units
V
V
V
V
µA
µA
µA
µA
853031AY
www.icst.com/products/hiperclocks.html
5
REV. B SEPTEMBER 16, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 5A to 5E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 5A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
R3
50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3 R4
125 125
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
84 84
3.3V
LVDS_Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK Receiv er
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
LVPECL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R3 R4
125 125
C1
C2
R5
100 - 200
R6
100 - 200
R1 R2
84 84
3.3V
CLK
nCLK HiPerClockS
Input
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
853031AY
www.icst.com/products/hiperclocks.html
11
REV. B SEPTEMBER 16, 2004
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS853031.PDF ] | |
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