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PDF ICS853014 Data sheet ( Hoja de datos )
| Número de pieza | ICS853014 | |
| Descripción | DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS853014 is a low skew, high performance • 5 differential LVPECL/ECL outputs
1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL
Fanout Buffer and a member of the HiPerClockS™
• 2 selectable differential LVPECL clock inputs
family of High Performance Clock Solutions • PCLKx, nPCLKx pairs can accept the following
from ICS. The ICS853014 has two selectable differential input levels: LVPECL, LVDS, CML, SSTL
clock inputs.
• Maximum output frequency: > 2GHz
Guaranteed output and part-to-part skew characteristics
make the ICS853014 ideal for those applications
demanding well defined performance and repeatability.
• Output skew: 13ps (typical)
• Part-to-part skew: 60ps (typical)
• Propagation delay: 460ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
nEN
PCLK0
nPCLK0
PCLK1
nPCLK1
CLK_SEL
00
11
D
Q
LE
VBB
PIN ASSIGNMENT
Q0 1
20 VCC
nQ0 2 19 nEN
Q1 3
18 VCC
nQ1 4 17 nPCLK1
Q0 Q2 5 16 PCLK1
nQ0
nQ2 6
15 VBB
Q3 7 14 nPCLK0
Q1 nQ3 8 13 PCLK0
nQ1
Q4 9 12 CLK_SEL
nQ4 10 11 VEE
Q2
nQ2
ICS853014
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.92mm package body
Q4
nQ4
G Package
Top View
853014BG
www.icst.com/products/hiperclocks.html
1
REV. C MAY 13, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol Parameter
-40°C
25°C
85°C
Units
Min Typ Max Min Typ Max Min Typ Max
VOH
VOL
VIH
VIL
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Input High Voltage
Common Mode Range; NOTE 2, 3
1.375
0.605
1.275
0.63
1.2
1.475
0.745
1.58
0.88
1.56
0.965
2.5
1.425
0.625
1.275
0.63
1.2
1.495 1.57
0.72 0.815
1.56
0.965
2.5
1.42 1.495 1.565
0.64 0.735 0.83
1.275
-0.83
0.63 0.965
1.2 2.5
V
V
V
V
V
IIH
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
150 150 150 µA
IIL
Input
PCLK0, PCLK1
Low Current nPCLK0, nPCLK1
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE
1:
Outputs
terminated
with
50Ω
to
V
CC
-
2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
µA
µA
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol Parameter
-40°C
Min Typ Max
25°C
Min Typ Max
85°C
Min Typ Max
VOH
VOL
VIH
VIL
VBB
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference;
NOTE 2
Input High Voltage
Common Mode Range;
NOTE 3, 4
-1.125
-1.895
-1.225
-1.87
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.44 -1.32
-1.075
-1.875
-1.225
-1.87
-1.005
-1.78
-0.93
-1.685
-0.94
-1.535
-1.44 -1.32
-1.08
-1.86
-1.225
-1.87
-1.44
-1.005
-1.765
-0.935
-1.67
-0.94
-1.535
-1.32
VEE+1.2V
0 VEE+1.2V
0 VEE+1.2V
0
IIH
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
150
150
150
IIL
Input
PCLK0, PCLK1
Low Current nPCLK0, nPCLK1
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE
2:
Single-ended
input
operation
is
limited.
V
CC
≥
3V
in
LVPECL
mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
Units
V
V
V
V
V
V
µA
µA
µA
853014BG
www.icst.com/products/hiperclocks.html
5
REV. C MAY 13, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853014 LVPECL buffer. Figure 6 shows a schematic example
of the ICS853014 LVPECL clock buffer. In this example, the in-
put is driven by an LVPECL driver. CLK_SEL is set at logic high
to select PCLK1/nPCLK1 input.
3.3V
Zo = 50
Zo = 50
LVPECL Driv er
3.3V
U1
R12 1K
3. 3V
C2
11
12
13
14
15
16
17
18
19
3.3V 20
VEE
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VCC
nEN
VCC
R9 R10
50 50
0.1u
C1
0.1u ICS853014
C5
0.1u
R 11
R7 1K
50
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
10
9
8
7
6
5
4
3
2
1
Zo = 50
Zo = 50
Zo = 50
Zo = 50
+
-
R2 R1
50 50
R3
50 C3
0.1u
+
-
R5 R4
50 50
R6
50 C4
0.1u
FIGURE 6. EXAMPLE ICS853014 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
853014BG
www.icst.com/products/hiperclocks.html
11
REV. C MAY 13, 2005
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS853014.PDF ] | |
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