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PDF ICS853011 Data sheet ( Hoja de datos )
| Número de pieza | ICS853011 | |
| Descripción | LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853011 is a low skew, high perfor-
ICS mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™ ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Perfor mance
Clock Solutions from ICS. The ICS853011
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-par t skew
characteristics make the ICS853011 ideal for those
clock distribution applications demanding well defined
perfor mance and repeatability.
FEATURES
• 2 differential 2.5V/3.3V LVPECL / ECL outputs
• 1 differential PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Output skew: 5ps (typical)
• Part-to-part skew: 130ps (maximum)
• Propagation delay: 390ps (maximum)
• Additive phase jitter, RMS: 0.06ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free compliant
packages
BLOCK DIAGRAM
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8 Vcc
7 PCLK
6 nPCLK
5 VEE
ICS853011
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
853011BM
www.icst.com/products/hiperclocks.html
1
REV. C JULY 13, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter
155.52MHz@12kHz to 20MHz
= 0.06ps (typical)
10k 100k 1M 10M
OFFSET FROM CARRIER FREQUENCY (HZ)
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853011BM
www.icst.com/products/hiperclocks.html
5
REV. C JULY 13, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853011.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 25mA = 95mW
• Power (outputs) = 30.94mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power (3.8V, with all outputs switching) = 95mW + 61.88mW = 156.88mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.157W * 103.3°C/W = 101.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
153.3°C/W
112.7°C/W
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853011BM
www.icst.com/products/hiperclocks.html
11
REV. C JULY 13, 2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS853011.PDF ] | |
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