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PDF ICS853001 Data sheet ( Hoja de datos )
| Número de pieza | ICS853001 | |
| Descripción | LVPECL/ECL BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS853001
1:1, DIFFERENTIAL LVPECL-TO-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
GENERAL DESCRIPTION
The ICS853001 is a 1:1 Differential LVPECL-
ICS to-LVPE C L B u f fe r a n d a m e m b e r o f t h e
HiPerClockS™ HiPerClock S ™family of High Perfor mance
Clock Solutions from ICS. The ICS853001
may be used to regenerate LVPECL clocks which
may have been attenuated, across a long trace, or may also
be used as a differential-to-LVPECL translator. The differen-
tial input can accept the following differential input types:
LVPECL, LVDS and CML. The device also has an output en-
able pin for debug/test purposes. When the output is disabled,
it drives differential LOW (Q = LOW, nQ = HIGH). The
ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP
or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on
space-constrained boards.
FEATURES
• 1:1 Differential LVPECL-to-LVPECL / ECL buffer
• 1 LVPECL clock output pair
• 1 Differential LVPECL PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
• Maximum output frequency: >2.5GHz
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• LVPECL mode operating voltage supply range:
V = 2.375V to 5.25V, V = 0V
CC EE
• ECL mode operating voltage supply range:
V = 0V, V = -5.25V to -2.375V
CC EE
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
OE D Q
PCLK
nPCLK
LE
V
BB
853001AG
PIN ASSIGNMENT
VCC 1
8 OE
Q2
7 PCLK
nQ 3
VEE 4
6 nPCLK
5 VBB
Q
ICS853001
nQ 8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
ICS853001
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 29, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, DIFFERENTIAL LVPECL-TO-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.03ps typical
10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853001AG
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 29, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, DIFFERENTIAL LVPECL-TO-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 6 shows an example of ICS853001 application schematic.
In this example, the device is operated at V = 3.3V. The
CC
decoupling capacitor should be located as close as possible to
the power pin.The input is driven by a 3.3V LVPECL driver. Only
one termination example is shown in this schematic. For more
termination approaches, please refer to the LVPECL Termina-
tion Application Note.
VCC
VCC
R7
133
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
R8
82.5
R5
133
R6
82.5
U1 ICS853001
5
6
VBB
7
8
nPCLK
PCLK
OE
VEE
nQ
Q
VCC
4
3
2
1
VCC
C5
0.1u
VCC=3.3V
VCC
R3
133
Zo = 50 Ohm
R1
133
-
Zo = 50 Ohm
+
R4
82.5
R2
82.5
FIGURE 6. APPLICATION SCHEMATIC EXAMPLE
853001AG
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 29, 2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS853001.PDF ] | |
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