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PDF LAN91C100FD Data sheet ( Hoja de datos )
| Número de pieza | LAN91C100FD | |
| Descripción | FEAST FAST ETHERNET CONTROLLER | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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Product Features
Dual Speed CSMA/CD Engine (10 Mbps and 100
Mbps)
Compliant with IEEE 802.3 100BASE-T
Specification
Supports 100BASE-TX, 100BASE-T4, and
10BASE-T Physical Interfaces
32 Bit Wide Data Path (into Packet Buffer
Memory)
Support for 32 and 16 Bit Buses
Support for 32, 16 and 8 Bit CPU Accesses
Synchronous, Asynchronous and Burst DMA
Interface Mode Options
128 Kbyte External Memory
LAN91C100FD REV. D
FEAST Fast Ethernet
Controller with Full
Duplex Capability
Datasheet
Built-In Transparent Arbitration for Slave
Sequential Access Architecture
Early TX, Early RX Functions
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
MII (Media Independent Interface) Compliant
MAC-PHY Interface Running at Nibble Rate
MII Management Serial Interface
Seven Wire Interface to 10 Mbps ENDEC
EEPROM-Based Setup
Full Duplex Capability
ORDERING INFORMATION
Order Numbers:
LAN91C100-FD for 208 Pin QFP Package
LAN91C100-FD for 208 Pin TQFP Package
SMSC DS – LAN91C100FD Rev. D
Page 1
PRELIMINARY
Rev. 10/14/2002
1 page  
FEAST Fast Ethernet Controller with Full Duplex Capability
Chapter 1 General Description
The LAN91C100FD is designed to facilitate the implementation of first generation Fast Ethernet adapters
and connectivity products. For this first generation of products, flexibility dominates over integration. The
LAN91C100FD is a digital device that implements the MAC portion of the CSMA/CD protocol at 10 and
100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure the CPU
to packet RAM data movement does not cause a bottleneck at 100 Mbps.
Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding
packets. The LAN91C100FD is software compatible with the LAN9000 family of products and can use existing
LAN9000 drivers (ODI, IPX, and NDIS) in 16 and 32 bit Intel X86 based environments.
Memory management is handled using a unique MMU (Memory Management Unit) architecture and a 32-
bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and
reception for superior data throughput and optimal performance. It also dynamically allocates buffer
memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from
performing these housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a
total chip storage (transmit and receive) of 64 outstanding packets.
FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus
Interface Unit (BIU) can handle synchronous as well as asynchronous buses, with different signals being
used for each one. FEAST's bus interface supports synchronous buses like the VESA local bus, as well
as burst mode DMA for EISA environments. Asynchronous bus support for ISA is supported even though
ISA cannot sustain 100 Mbps traffic. Fast Ethernet could be adopted for ISA-based nodes on the basis of
the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first is a conventional seven wire ENDEC
interface that connects to the LAN83C694 for 10BASE-T and coax 10 Mbps Ethernet networks. The second
interface follows the MII (Media Independent Interface) specification draft standard, consisting of 4 bit wide
data transfers at the nibble rate. This interface is applicable to 10 Mbps or 100 Mbps networks. Three of the
LAN91C100FD’s pins are used to interface to the two-line MII serial management protocol. Four I/O ports
(one input and three output pins) are provided for LAN83C694 configuration.
The LAN91C100FD is based on the LAN91C100 FEAST, functional revision G modified to add full duplex
capability. Also added is a software-controlled option to allow collisions to discard receive packets.
Previously, the LAN91C100 supported a “Diagnostic Full Duplex” mode. Under this mode the transmit
packet is looped internally and received by the MAC. This mode was enabled using the FDUPLX bit in the
TCR. In order to avoid confusion, the new, broader full duplex function of the LAN91C100FD is
designated as Switched Full Duplex, and the TCR bit enabling it is designated as SWFDUP. When the
LAN91C100FD is configured for SWFDUP, its transmit and receive paths will operate independently and
some CSMA/CD functions will be disabled. When the controller is not configured for SWFDUP it will follow
the CSMA/CD protocol.
SMSC DS – LAN91C100FD Rev. D
Page 5
PRELIMINARY
Rev. 10/14/2002
5 Page 
FEAST Fast Ethernet Controller with Full Duplex Capability
PQFP/TQFP
PIN NO.
20, 21, 22,
24
198
196
192
11
NAME
Receive
Data
Manage-
ment Data
Input
Manage-
ment Data
Output
Manage-
ment
Clock
Receive
Error
SYMBOL
RXD0-
RXD3
MDI
MDO
MCLK
RX_ER
7
nChip
nCSOUT
Select
Output
8 nReceive nRXDISC
Packet
Discard
37 RDMAH
BUFFER
TYPE
I
I with
pulldown
DESCRIPTION
Inputs. Received Data nibble from MII PHY.
These pins are ignored when MIISEL is low.
MII management data input.
O4 MII management data output.
O4 MII management clock.
I with
pulldown
O4
I with
pullup
O4
Input. Indicates a code error detected by PHY.
Used by the LAN91C100FD to discard the
packet being received. The error indication
reported for this event is the same as a bad CRC
(Receive Status Word bit 13). This pin is
ignored when MIISEL is low.
Output. Chip Select provided for mapping of
PHY functions into LAN91C100FD decoded
space. Active on accesses to LAN91C100FD’s
eight lower addresses when the BANK
SELECTED is 7.
Input. Used to discard the receive packet being
stored in memory. Assertion of the pin during a
packet reception results in the interruption of
packet reception into memory. The memory
allocated to the packet and the packet number in
use are freed. The input is driven
asynchronously and is synchronized internally by
the LAN91C100FD. Pin assertion may take
place at any time during the receive DMA
packet. The assertion has no effect if there is no
packet being DMAed to memory or if asserted
during the last DMA write to memory. Works for
both MII and ENDEC. The typical use of
nRXDISC is with the LAN91C100FD in PRMS
mode with an external associative memory use
for address filtering. *Note: The pin must be
asserted for a minimum of 80ns.
Output. Active when the first dword of the
address is written (RCVDMA=1, RA10-RA4=0,
RA3-RA2=X).
Buffer Types
O4 Output buffer with 2mA source and 4mA sink
O12 Output buffer with 6mA source and 12mA sink
O16 Output buffer with 8mA source and 16mA sink
O24 Output buffer with 12mA source and 24mA sink
OD16
Open drain buffer with 16mA sink
SMSC DS – LAN91C100FD Rev. D
Page 11
PRELIMINARY
Rev. 10/14/2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN91C100FD.PDF ] | |
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