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PDF GLT441L08 Data sheet ( Hoja de datos )

Número de pieza GLT441L08
Descripción 512K X 8 CMOS DYNAMIC RAM
Fabricantes G-Link 
Logotipo G-Link Logotipo



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G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Features :
Description :
524,288 words by 8 bits organization.
The GLT44108 is a 524,288 x 8 bit high-
Fast access time and cycle time.
performance CMOS dynamic random access
Low power dissipation.
memory. The GLT44108 offers Fast Page mode with
Operating Current-150mA max.
asymmetric address and accepts 512-cycle refresh in
TTL Standby Current-2mA max.
8ms interval.
All inputs are TTL compatible. Fast Page Mode
Read-Modify-Write, RAS -Only Refresh, operation allows random access up to 512 x 8 bits
CAS -Before- RAS Refresh, Hidden
within a page, with cycle times as short as 22ns.
Refresh and Test Mode Capability.
The GLT44108 is best suited for graphics, digital
1024 refresh cycles/16ms.
signal processing and high performance peripherals.
Available in 28pin 400 mil SOJ
Single +5.0V±10% Power Supply.
All inputs and Outputs are TTL-
compatible.
Fast Page Mode supports sustained data
rates up to 50MHZ.
PIN CONFIGURATION :
Vcc
DQ0
DQ1
DQ2
DQ3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
GLT44108
28 Lead SOJ
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VSS
DQ7
DQ6
DQ5
DQ4
CAS
OE
NC
A8
A7
A6
A5
A4
VSS
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-1-
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

1 page




GLT441L08 pdf
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
AC Characteristics (0°CTA70°C,See note 1,2)
Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.0V/0.8V
Parameter
40 ns
50 ns
Symbol MIN. MAX. MIN. MAX.
Read/Write Cycle Time
tRC 75 - 90 -
Read Midify Write Cycle Time
tRWC
120 -
140 -
Access Time from RAS
tRAC - 40 - 50
Access Time from CAS
tCAC - 12 - 13
Access Time from Column Address
tAA
- 20 - 25
CAS to Output in Low-Z
tCLZ 0 - 0 -
Output Buffer Turn-off Delay from CAS tOFF
0 8 0 10
Transition Time(Rise and Fall)
RAS Precharge Time
tT 3 50 3 50
tRP 25 - 30 -
RAS Pulse Width
tRAS 40 10000 50 10000
RAS Hold Time
tRSH 12 - 13 -
CAS Hold Time
tCSH 40 - 50 -
CAS Pulse Width
tCAS 12 10000 13 10000
RAS to CAS Delay Time
tRCD 16 30 18 37
RAS to Column Address Delay Time
tRAD
11 22 13 25
CAS to RAS Precharge Time
tCRP 5 - 5 -
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time Referenced
tASR
tRAH
tASC
tCAH
tAR
0-0-
6-8-
0-0-
6-8-
30 - 40 -
to RAS
Column Address Lead Time Referenced tRAL
20 - 25 -
to RAS
Read Command Setup Time
Read Command Hold Time Referenced
tRCS
tRRH
0-0-
0-0-
to RAS
Read Command Hold Time Referenced tRCH
0-0-
to CAS
WE Hold Time Referenced to CAS
Write Command Hold Time Referenced
tWCH
tWCR
6-
30 -
7-
40 -
to RAS
60 ns
MIN. MAX. Unit
110 -
ns
160 -
ns
- 60 ns
- 15 ns
- 30 ns
0 - ns
0 13 ns
3 50 ns
40 - ns
60 10000 ns
15 - ns
60 - ns
15 10000 ns
20 45 ns
15 30 ns
5 - ns
0 - ns
10 - ns
0 - ns
10 - ns
45 - ns
30 - ns
0 - ns
0 - ns
0 - ns
10 - ns
45 - ns
Notes
3,4
3,4
3,4
3
7
2
4
4
8
9
9
10
5
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-5-
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

5 Page





GLT441L08 arduino
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Fast Page Mode Late Write Cycle
VIH-
RAS
VIL-
VIH-
CAS
VIL-
tCRP
tCSH
tRCD
tCAS
tASR
tRAD
tCAH
tRAH tASC
tRASP
tRHCP
tPC
tCP tCAS tCP
tRSH
tCAS
tASC
tCAH
tASC
tRAL
tCAH
VIH-
Address
VIL-
VIH-
WE
VIL-
ROW
ADDR.
COLUMN
ADDRESS
tRCS
tCWL
tWP
COLUMN
ADDRESS
tRCS
tCWL
tWP
COLUMN
ADDRESS
tRCS
tCWL
tRWL
tWP
tOEH
tOEH
tOEH
VIH-
OE
VIL-
tOED tDS tDH
tOED tDS tDH
tOED tDS tDH
VIH-
DQ
VIL-
Hi-Z
VALID
DATA-IN
Hi-Z
VALID
DATA-IN
Hi-Z
VALID
DATA-IN
tRP
tCRP
Fast Page Read - Modify - Write Cycle
VIH-
RAS
VIL-
tCSH
tRASP
tRCD
VIH-
CAS
VIL-
tASR
tRAD
tRAH
tASC
tCAH
VIH-
Address
VIL-
ROW
ADDR.
COL.
ADDR.
tCAS
VIH-
WE
VIL-
tRCS
tCWD
tAWD
tRSH
tCP tCAS
tASC
tCAH
COL.
ADDR.
tCWL
tPRWC
tRAL
tWP tCWD
tAWD
tCPWD
VIH-
OE
VIL-
VI/OH-
DQ
VI/OL-
tRWD
tOEA
tCAC
tAA
tRAC
tOED
tOEZ tDS
tDH
tOEA
tCAC
tAA
tOED
tOEZ
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
tCLZ
VALID
DATA-OUT
Don't Care
tRP
tCRP
tRWL
tCWL
tWP
tOEH
tDH
tDS
VALID
DATA-IN
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
- 11 -
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

11 Page







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