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PDF SC1486 Datasheet ( Hoja de datos )

Número de pieza SC1486
Descripción Dual Synchronous Buck Pseudo Fixed Frequency DDR Power Supply Controller
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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SC1486 Hoja de datos, Descripción, Manual
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SC1486
Dual Synchronous Buck Pseudo Fixed
Frequency DDR Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC1486 is a dual output constant on synchronous-
buck PWM controller optimized for cost effective mobile
DDR applications. Features include high efficiency, a fast
dynamic response with no minimum on time, a REFIN
input and a buffered REFOUT pin capable of sourcing
3mA. The excellent transient response means that
SC1486 based solutions will require less output
capacitance than competing fixed frequency converters.
The frequency is constant until a step in load or line voltage
occurs at which time the pulse density and frequency will
increase or decrease to counter the change in output or
input voltage.
The output voltage of the first controller can be adjusted
from 0.5V to VCCA. In DDR applications, this voltage is
set to 2.5 volts. A resistor divider from the 2.5 volt supply
is used to drive the REFIN pin of the second controller. A
unity gain buffer drives the REFOUT pin to the same
potential as REFIN. The second controller regulates its
output to REFOUT. Two frequency setting resistors set
the on-time for each buck controller. The frequency can
thus be tailored to minimize crosstalk. The integrated
gate drivers feature adaptive shoot-through protection
and soft switching. Additional features include cycle-by-
cycle current limit, digital soft-start, overvoltage and
under-voltage protection, and a PGOOD output for each
controller.
Typical Application Circuit
‹ Constant on-time for fast dynamic response
‹ VIN range = 1.8V – 25V
‹ DC current sense using low-side RDS(ON) sensing
or sense resistor
‹ Integrated reference buffer for VTT
‹ Low power S3 state
‹ Resistor programmable frequency
‹ Cycle-by-cycle current limit
‹ Digital soft-start
‹ PSAVE option for VDDQ
‹ Over-voltage/under-voltage fault protection
‹ <20uA shutdown current
‹ Low quiescent power dissipation
‹ Two separate PGOOD indicators
‹ Separate enable of each switcher
‹ Integrated gate drivers with soft switching
‹ Efficiency >90%
‹ 1% Internal reference
‹ 28 Lead TSSOP
‹ Industrial temperature range
Applications
‹ Notebook computers
‹ CPU I/O supplies
‹ Handheld terminals and PDAs
‹ LCD monitors
‹ Network power supplies
VDDQ/2
VBAT
VDDQ, 2.5V
R11
R10
L1
+ C7
R4
PGND1
R5
R1
R2
REFOUT
EN1
Q1
R3
Q2
23 TON1
9 TON2
8 REFIN
10 REFOUT
22 EN/PSV1
6 DH1
5 LX1
4 ILIM1
2 DL1
1 PGND1
SC1486
PGOOD1 27
PGOOD2 13
DH2 20
LX2 19
ILIM2 18
DL2 16
PGND2 15
FBK2 12
FBK1 26
PGOOD2
PGOOD1
Q4
R8
Q3
VBAT
L2
+ C8
PGND1
VTT, 1.25V
Revision 3, October 2002
1
www.semtech.com

1 page

SC1486 pdf
SC1486
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M
Parameter
Conditions
25°C
-40°C to 125°C Units
Min Typ Max Min Max
Gate Drivers
Shoot-Through Delay (4)
DH or DL rising
30
ns
DL Pull-Down Resistance
DL Pull-Up Resistance
DH Pull-Down Resistance
DH Pull-Up Resistance
DL low
DL high
DH low, BST - LX = 5V
DH high, BST - LX = 5V
0.8
2
2
2
1.6
4
4
4
Notes:
(1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage.
(2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(4) Guaranteed by design. See Shoot-Through Delay Timing Diagram below.
Shoot-Through Delay Timing Diagram
LX
DH
DL
tplhDL
DL
tplhDH
2002 Semtech Corp.
5
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SC1486 arduino
SC1486
POWER MANAGEMENT
Application Information (Cont.)
Power Good Output
Each controller has its own PGOOD. Power good is an
open-drain output and requires a pull-up resistor. When
the output voltage is 10% above or below its set voltage,
PGOOD gets pulled low. It is held low until the output
voltage returns to within 10% of the output set voltage.
PGOOD is also held low during start-up and will not be
allowed to transition high until soft start is over and the
output reaches 90% of its set voltage. There is a 2us
delay built into the PGOOD circuit to prevent false transi-
tions.
Output Overvoltage Protection
When the output exceeds 10% of the its set voltage the
low-side MOSFET is latched on. It stays latched and the
SMPS is off until the enable input, REFIN or VCCA is
toggled. There is a 2us delay built into the OV protection
circuit to prevent false transitions. A OV fault in either
controller will not cause the other one to shutdown. Note:
to reset VDDQ from a fault, VCCA1 or EN/PSV must be
togled. To reset VTT from a fault, VCCA2 or REFIN must
be togled.
Output Undervoltage Protection
When the output is 30% below its set voltage the output
is latched in a tristated condition, and the SMPS is off
until the enable input is toggled. There is a 2us delay
built into the UV protection circuit to prevent false transi-
tions. An UV fault in either controller will not effect the
other controller.
POR, UVLO and Softstart
An internal power-on reset (POR) occurs when VCCA1 and
VCCA2 exceed 3V, resetting the fault latch and soft-start
counter, and preparing the PWM for switching. VCCA
undervoltage lockout (UVLO) circuitry inhibits switching
and forces the DL gate driver high until VCCA rises above
4.2V. At this time the circuit will come out of UVLO and
begin switching, and the softstart circuit being enabled,
will progressively limit the output current over a prede-
termined time period. The ramp occurs in four steps: 25%,
50%, 75% and 100%, thereby limiting the slew rate of
the output voltage. There is 100mV of hysteresis built
into the UVLO circuit and when the VCCA falls to 4.1V the
output drivers are shutdown and tristated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder-
ate-sized high-side, and larger low-side power MOSFETs.
An adaptive dead-time circuit monitors the DL output and
prevents the high-side MOSFET from turning on, until DL
is fully off, and conversely, monitors the DH output and
prevents the low-side MOSFET from turning on until DH
is fully off. Be sure there is low resistance and low induc-
tance between the DH and DL outputs to the gate of
each MOSFET.
Design Procedure
Prior to any design of a switch mode power supply (SMPS)
for notebook computers, determination of input voltage,
load current, switching frequency and inductor ripple cur-
rent must be specified.
Input Voltage Range
The maximum input voltage (VINMAX) is determined by the
highest AC adaptor voltage. The minimum input voltage
(VINMIN) is determined by the lowest battery voltage after
accounting for voltage drops due to connectors, fuses
and battery selector switches.
Maximum Load Current
There are two values of load current to consider. Con-
tinuous load current and peak load current. Continuous
load current has more to do with thermal stresses and
therefore drives the selection of input capacitors,
MOSFETs and commutation diodes. Whereas, peak load
current determines instantaneous component stresses
and filtering requirements such as, inductor saturation,
output capacitors and design of the current limit circuit.
Switching Frequency
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a func-
tion of VIN2. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up.
Inductor Ripple Current
Low inductor values create higher ripple current, result-
ing in smaller size, but are less efficient because of the
high AC currents flowing through the inductor. Higher in-
ductor values do reduce the ripple current and are more
efficient, but are larger and more costly. The selection of
the ripple current is based on the maximum output cur-
rent and tends to be between 20% to 50% of the maxi-
mum load current. Again, cost, size and efficiency all play
a part in the selection process.
2002 Semtech Corp.
11
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