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PDF SC1485 Datasheet ( Hoja de datos )

Número de pieza SC1485
Descripción Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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SC1485 Hoja de datos, Descripción, Manual
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SC1485
Dual Synchronous Buck Pseudo Fixed
Frequency Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC1485 is a dual output constant on synchronous-
buck PWM controller intended for use in notebook
computers and other battery operated portable devices.
Features include high efficiency and a fast dynamic
response with no minimum on time. The excellent
transient response, means that SC1485 based solutions
will require less output capacitance than competing fixed
frequency converters.
The frequency is constant until a step in load or line voltage
occurs at which time the pulse density and frequency will
increase or decrease to counter the change in output or
input voltage. After the transient event, the controller
frequency will return to steady state operation. At light
loads, Power-Save Mode enables the SC1485 to skip
PWM pulses for better efficiency.
Each output voltage can be independently adjusted from
0.5V to VCCA. Two frequency setting resistors set the
on-time for each buck controller. The frequency can thus
be tailored to minimize crosstalk. The integrated gate
drivers feature adaptive shoot-through protection and
soft switching. Additional features include cycle-by-cycle
current limit, digital soft-start, over-voltage and under-
voltage protection, and a PGOOD output for each
controller.
Typical Application Circuit
Constant on-time for fast dynamic response
Programmable VOUT range = 0.5 – VCCA
VIN Range = 1.8V – 25V
DC current sense using low-side RDS(ON)
sensing or sense resistor
Resistor programmable frequency
Cycle-by-cycle current limit
Digital soft-start
Separate PSAVE option for each switcher
Over-voltage/Under-voltage fault protection
10uA Typical shutdown current
Low quiescent power dissipation
Two PGOOD indicators
1% Reference (2% system DC accuracy)
Efficiency >90%
Integrated gate drivers with soft switching
Separate enables
28 Lead TSSOP
Industrial temperature range
Applications
Notebook computers
CPU I/O supplies
Handheld terminals and PDAs
LCD monitors
Network power supplies
VBAT
VOUT1
L1
+ C7
R4
R1
R2
EN2
EN1
Q1
R3
Q2
PGND1
R5
23 TON1
9 TON2
8 EN/PSV2
22 EN/PSV1
6 DH1
5 LX1
4 ILIM1
2 DL1
1 PGND1
SC1485
PGOOD1 27
PGOOD2 13
PGOOD1
PGOOD2
VBAT
DH2 20
LX2 19
ILIM2 18
DL2 16
PGND2 15
FBK2 12
FBK1 26
R8
Q4
L2
Q3
+ C8
PGND1
VOUT2
R7
R6
Revision: October 14, 2004
1
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1 page

SC1485 pdf
POWER MANAGEMENT
Pin Configuration
Top View
SC1485
Ordering Information
Device
Package(1)
SC1485ITSTR
TSSOP-28
SC1485ITSTRT(2)
TSSOP-28
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
TSSOP-28
Pin Descriptions
Pin # Pin Name Pin Function
1 PGND1 Power ground.
2 DL1 Gate drive output for the low side MOSFET switch.
3 VDDP1 +5V supply voltage input for the gate drivers.
4 ILIM1 Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source
for resistor sensing through a threshold sensing resistor. See applications section for more
information.
5 LX1 Switching node inductor connection.
6 DH1 Gate drive output for the high side MOSFET switch.
7 BST1 Boost capacitor connection for the high side gate drive.
8 EN/PSV2 Enable/Power Save input pin. Tie to ground to disable SMPS. Tie to +5V to enable SMPS and
activate PSAVE mode. Float to Enable SMPS and activate continous conduction mode.
9 TON2 Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply
and VIN.
10 VOUT2 Output voltage sense input for the SMPS output. Connect to the output of the SMPS.
11 VCCA2 Supply voltage input for the analog supply. Connect through a RC filter.
12 FBK2 Feedback input for the SMPS. Connect from resistive divider at output to select output voltage
from 0.5V to VCCA.
13 PGOOD2 Power Good output. Goes high after a fixed clock cycle delay following power up.
14 AGND2 Analog ground.
2004 Semtech Corp.
5
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5 Page

SC1485 arduino
SC1485
POWER MANAGEMENT
Applications Information (Cont.)
Stability Considerations
Unstable operation shows up in two related but dis-
tinctly different ways: double pulsing and fast-feedback
loop instability.
Double-pulsing occurs due to noise on the output or be-
cause the ESR is too low, causing not enough voltage
ramp in the output signal. This causes the error amplifier
to trigger prematurely after the 400ns minimum off-time
has expired. Double-pulsing will result in higher ripple
voltage at the output, but in most cases is harmless.
However, in some cases double-pulsing can indicate the
presence of loop instability, which is caused by insuffi-
cient ESR. One simple way to solve this problem is to add
some trace resistance in the high current output path. A
side effect of doing this is output voltage droop with load.
Another way to eliminate doubling-pulsing is to add a 10pF
capacitor across the upper feedback resistor divider
network. This is shown below in Figure 5, by capacitor
C4 in the schematic. This capacitance should be left out
until confirmation that double-pulsing exists. Adding this
capacitance will add a zero in the transfer function and
should eliminate the problem. It is best to leave a spot
on the PCB in case it is needed.
SC1485 ESR Requirements
The constant on-time control used in the SC1485
regulates the ripple voltage at the output capacitor. This
signal consists of a term generated by the output ESR of
the capacitor and a term based on the increase in voltage
across the capacitor due to charging and discharging
during the switching cycle. The minimum ESR is set to
generate the required ripple voltage for regulation. For
most applications the minimum ESR ripple voltage is
dominated by PCB layout and the properties of SP or
POSCAP type output capacitors. For applications using
ceramic output capacitors the absolute minimum ESR
must be considered. Existing literature describing the ESR
requirements to prevent double pulsing does not
accurately predict the performance of constant on-time
controllers. A time domain model of the converter was
developed to generate equations for the minimum ESR
empirically. If the ESR is low enough the ripple voltage is
dominated by the charging of the output capacitor. This
ripple voltage lags the on-time due to the LC poles and
can cause double pulsing if the phase delay exceeds the
off-time of the converter. Refering to Figure 5, the
equation for the minimum ESR as a function of output
capacitance and switching frequency and duty cycle is;
BST
DH
LX
ILIM
VDDP
DL
PGND
7
6
5
4
3
2
1
+5V +VIN
+
D1 C1
Q1
C2
L1
R1
D2
Q2
+
C3
ESR
>

R2+R3
R3

•

1+
3

Fs
-200000
Fs

2•π•Cout Fs ( 1 D) 2


0.5V - 5.5V
R2 C4
10pF
Where D = Vout/Vin.
R3
FBK
FIGURE 5
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
The best way for checking stability is to apply a zero to
full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Over one cycle of
ringing after the initial step is sign that the ESR should
be increased.
2004 Semtech Corp.
11
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