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Número de pieza | S5935 | |
Descripción | PCI 5V Bus Master/Target Device 32-bit | |
Fabricantes | AMCC | |
Logotipo | ||
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APPLIED MICRO CIRCUITS CORPORATION
S5935
PCI PRODUCT
DATA BOOK
For Marketing and Application Information Contact:
Applied Micro Circuits Corporation
6290 Sequence Drive
San Diego, CA 92121-4358
(800) 755-2622
(619) 450-9333
Fax (619) 450-9885
http://www.amcc.com
1 page Target Disconnects .................................................................................................................. 7-92
Target Requested Retries ........................................................................................................ 7-93
Target Aborts ........................................................................................................................... 7-93
PCI Bus Mastership ........................................................................................................................... 7-95
Bus Mastership Latency Components ..................................................................................... 7-95
Bus Arbitration ......................................................................................................................... 7-95
Bus Acquisition ........................................................................................................................ 7-96
Target Latency ......................................................................................................................... 7-96
Target Locking ......................................................................................................................... 7-96
PCI Bus Interrupts ............................................................................................................................... 7-98
PCI Bus Parity Errors .......................................................................................................................... 7-98
8. ADD-ON BUS INTERFACE .................................................................................................................... 8-99
Add-On Operation Register Accesses ................................................................................................ 8-99
Add-On Interface Signals ........................................................................................................ 8-99
System Signals ........................................................................................................................ 8-99
Register Access Signals .......................................................................................................... 8-99
Asynchronous Register Accesses ......................................................................................... 8-100
Synchronous FIFO and Pass-Thru Data Register Accesses ................................................. 8-100
nv Memory Accesses Through the Add-On General Control/Status Register ....................... 8-100
Mailbox Bus Interface ....................................................................................................................... 8-100
Mailbox Interrupts .................................................................................................................. 8-103
FIFO Bus Interface ............................................................................................................................ 8-103
FIFO Direct Access Inputs ..................................................................................................... 8-103
FIFO Status Signals .............................................................................................................. 8-103
FIFO Control Signals ............................................................................................................. 8-103
Pass-Thru Bus Interface ................................................................................................................... 8-103
Pass-Thru Status Indicators .................................................................................................. 8-104
Pass-Thru Control Inputs ....................................................................................................... 8-104
Non-Volatile Memory Interface .......................................................................................................... 8-104
Non-Volatile Memory Interface Signals ................................................................................. 8-104
Accessing Non-Volatile Memory ............................................................................................ 8-105
nv Memory Device Timing Requirements .............................................................................. 8-107
9. MAILBOX OVERVIEW ......................................................................................................................... 9-109
Functional Description ...................................................................................................................... 9-109
Mailbox Empty/Full Conditions ............................................................................................... 9-110
Mailbox Interrupts ................................................................................................................... 9-110
Add-On Outgoing Mailbox 4, Byte 3 Access ........................................................................... 9-110
Bus Interface ...................................................................................................................................... 9-111
PCI Bus Interface ................................................................................................................... 9-111
Add-On Bus Interface ............................................................................................................. 9-111
8-Bit and 16-Bit Add-On Interfaces ......................................................................................... 9-111
Configuration ...................................................................................................................................... 9-112
Mailbox Status ........................................................................................................................ 9-112
Mailbox Interrupts ................................................................................................................... 9-113
iii
5 Page ARCHITECTURAL OVERVIEW
Table 1. PCI Configuration Registers
Byte 3
Byte 2
Byte 1
Byte 0
Device ID
Vendor ID
PCI Status
PCI Command
Class Code
Revision ID
Built-in Self Test Header Type Latency Timer Cache Line Size
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Reserved
Reserved Space
Reserved Space
Expansion ROM Base Address
Reserved Space
Reserved Space
Max. Latency Min. Grant Interrrupt Pin Interrupt Line
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
Table 2. PCI Operation Registers
PCI Operation Registers
Outgoing Mailbox Register 1 (OMB1)
Outgoing Mailbox Register 2 (OMB2)
Outgoing Mailbox Register 3 (OMB3)
Outgoing Mailbox Register 4 (OMB4)
Incoming Mailbox Register 1 (IMB1)
Incoming Mailbox Register 2 (IMB2)
Incoming Mailbox Register 3 (IMB3)
Incoming Mailbox Register 4 (IMB4)
FIFO Register Port (bidirectional) (FIFO)
Master Write Address Register (MWAR)
Master Write Transfer Count Register (MWTC)
Master Read Address Register (MRAR)
Master Read Transfer Count Register (MRTC)
Mailbox Empty/Full Status Register (MBEF)
Interrupt Control/Status Register (INTCSR)
Bus Master Control/Status Register (MCSR)
S5935
Address
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
PCI Operation Registers
The second group of registers are the PCI Operation
Registers shown in Table 2. This group consists of
sixteen 32-bit (DWORD) registers accessible to the
Host processor from the PCI Local bus. These are the
main registers through which the PCI Host configures
S5935 operation and communicates with the Add-On
Local bus. These registers encompass the PCI bus
incoming and outgoing Mailboxes, FIFO data channel,
Bus Master Address and Count registers, Pass-Thru
data channel registers and S5935 device Status and
Control registers.
Add-On Bus Operation Registers
The third and last register group consists of the Add-On
Operation Registers, shown in Table 3. This group of
eighteen 32-bit (DWORD) registers is accessible to the
Add-On Local bus. These are the main registers through
which the Add-On logic configures S5935 operation
and communicates with the PCI Local bus. These
registers encompass the Add-On bus Mailboxes, Add-
On FIFO, DMA Address/Count Registers (when Add-
On initiated Bus Mastering), Pass-Thru Registers and
Status/Control registers.
Non-Volatile Memory Interface
The S5935 contains a set of PCI Configuration Regis-
ters. These registers can be initialized with default
values or with designer specified values contained in an
external nvRAM. The nvRAM can be either a serial (2
Kbytes, maximum) or a byte-wide device (64 Kbytes,
maximum).
The optional nvRAM allows the Add-On card manufac-
turer to initialize the S5935 with his specific Vendor ID
and Device ID numbers along with desired S5935
operation characteristics. The non-volatile memory fea-
ture also provides for the Expansion BIOS and POST
code (power-on-self-test) options on the PCI bus.
1-3
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet S5935.PDF ] |
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