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PDF CS1088 Data sheet ( Hoja de datos )

Número de pieza CS1088
Descripción Vacuum Fluorescent Display Tube Driver
Fabricantes ON Semiconductor 
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CS1088
Vacuum Fluorescent
Display Tube Driver
The VFD Driver is a microprocessor interface IC that drives a
multiplexed VF (Vacuum Fluorescent) display tube. It consists of a
34–bit shift register, a 34–bit transparent data latch, a metal mask
ROM, six 20 mA anode output drivers, twenty–five 2 mA anode
output drivers, and three 50 mA grid drivers with output enables.
http://onsemi.com
Features
Power On Reset
Display Dimming Possible
Three, 50 mA Grid Drivers
Anodes:
6 @ 20 mA
25 @ 2 mA
VIGN 12 V
Regulator
5V
GND
VBAT
VCC
µP
PORT
PORT
PORT
GND PORT
Chip Select
Clock
SPI Functions
0.1 µF VBB
CS1088
Anodes
1:31
FILAMENT
VFD
GRID1GRID2 GRID3 GND
DIN GRID1
CLK GRID2
STB GRID3
GREN
GND
40
1
DIP–40
WIDE BODY
N SUFFIX
CASE 711
ORDERING INFORMATION*
Device
CS1088XN40
Package
DIP–40
WIDE BODY
Shipping
9 Units/Rail
*For additional package options, consult your local
ON Semiconductor sales office.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Figure 1. Application Diagram
© Semiconductor Components Industries, LLC, 2001
August, 2001 – Rev. 9
1
Publication Order Number:
CS1088/D

1 page




CS1088 pdf
CS1088
GRID1 GRID2 GRID3 AN1 AN2 AN3
AN25 AN26 AN27 AN28 AN29 AN30 AN31
VBB
GND
POR
VREG
VREG
GREN
VREG
STB
VREG
DIN
VREG
CLK
VREG
METAL MASK ROM
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ
LE
DQ DQ
LE LE
DQ
LE
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
DQ
CLK
R
Output Drive Capability
Grid Outputs: 50 mA
AN24 – AN29: 20 mA
AN1 – AN23, AN30, AN31: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the DIN pin at the rising
edge of the CLK input. Thirty four bits of data are capable
of being stored by the shift register. Once the desired pattern
is stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN31 are always enabled.
http://onsemi.com
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