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PDF VSC9210 Data sheet ( Hoja de datos )
| Número de pieza | VSC9210 | |
| Descripción | 2.488 Gbits/sec SONET/SDH FEC Encoder and Decoder (CODEC) Chipset | |
| Fabricantes | Vitesse Semiconductor | |
| Logotipo |  |
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VITESSE
SEMICONDUCTOR CORPORATION
dvance Product Information
VSC9210
2.488 Gbits/sec SONET/SDH
FEC Encoder and Decoder (CODEC) Chipset
Features
• Reed-Solomon Encoding and Decoding using a
(255,241) code
• Realizes a Decoder Output BER of 10-20 for Input
BER of 10-5
• Processes Data rates up to 2.654 Gbps and Infor-
mation rates to 2.488 Gbps
• Device pin configured as stand-alone Encoder,
Decoder, or Bypass with clocks disabled
• Provides a dedicated user defined data channel at
10.368 Mbps
• Provides count of correctable 0’s and 1’s that are
in error in prior Code Word
• Operable at OC-48, OC-12, OC-3 rates
• Interfaces directly with Vitesse OC-48 rate
components
• PECL and TTL I/O
• Telecom Temperature range: 0 - 85C Case
• Maximum power 1.05W (Encoder), 2.82W
(Decoder @ 10-5 Input BER), 0.74W
(Bypass)
• +3.3V Power Supply
• Thermally Enhanced 208 PQFP Package
VSC9210 Block Diagram
VCXO_CLK+/-
DATAIN[15:0]+/-
INCLK+/-
USER_CHANNEL[7:0]
FEC Bypass
RS Encoder
Phase
Detector
VCXO_UPN
VCXO_DOWNN
UP_TRI
DOWN_TRI
PD_REF
VCXO_REF
DATAOUT[15:0]+/-
LOOP_CLK+/-
MODE
BYPASS
RESET
REFRAME
TST_CTL[1:0]
FEC
Framer
RS Decoder
LOCK FP
Error Monitor
OUTCLK+/-
USER_CLK
ECC_FLAG
ECC[5:0]
G52256-0, Rev. 2.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
1 page  
VITESSE
SEMICONDUCTOR CORPORATION
dvance Product Information
VSC9210
2.488 Gbits/sec SONET/SDH
FEC Encoder and Decoder (CODEC) Chipset
Signal Definitions
Signal
DATAIN[15:0] +/-
INCLK +/-
DATAOUT[15:0] +/-
OUTCLK +/-
LOOP_CLK +/-
Name
I/O
Freq/
Type
Description
155/166
Mbs
This parallel data bus receives the incoming
STS-48 at 155MHz (or Encoded data at 166
MHz). DATAIN[15] is the most significant bit
Parallel Receive Data. I
and DATAIN[0] is the least significat bit.
DATAIN[15] corresponds to the first arriving bit
PECL
on the serial data stream. DATAIN[15:0] is
sampled on the rising edge of INCLK.
Parallel Receive Data
Clock.
I
155/166
MHz
This clock reference is used to capture the
Parallel Receive Data on the rising edge. The
clock frequency is 155.52MHz relating to STS-
48 for Encoder operation; 165.888MHz for
Decoder operation (16/15 ratio).
PECL
166/155 This parallel data bus outputs the Encoded Data
Mbs at 166MHz (or Decoded STS-48 data at
155MHz). DATAOUT[15] is the most significant
Parallel Transmit Data O
bit and DATAOUT[0] is the least significat bit.
DATAOUT[15] corresponds to the first
transmitted bit on the serial data stream.
PECL
This clock reference is used to output the Parallel
166/155 Transmit Data on the falling edge after Encode
Parallel Transmit Data
Clock.
I
MHz
or Decode operation is complete. The clock
frequency is 166.888MHz for Encoder
operation; 155.52MHz relating to STS-48 for
PECL Decoder operation (15/16 ratio).
This clock is used by the receiving device to
Parallel Transmit Data
Loopback Clock.
O
166/155
MHz
capture DATAOUT[15:0] on the rising edge. It is
an inverted version of the received OUTCLK
input signal.
PECL
MODE
Mode Control
Static control pin to set device to Encoder or
STATIC Decoder operation (when not in Bypass mode;
BYPASS = 0). MODE = 0 for Encoder, MODE =
I 1 for Decoder. Signal has internal pulldown.
TTL
G52256-0, Rev. 2.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet VSC9210.PDF ] | |
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