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PDF ZL30109 Data sheet ( Hoja de datos )
| Número de pieza | ZL30109 | |
| Descripción | DS1/E1 System Synchronizer | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL30109
DS1/E1 System Synchronizer with
19.44 MHz Output
Data Sheet
Features
October 2004
• Supports Telcordia GR-1244-CORE Stratum 4 and
Stratum 4E
Ordering Information
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
ZL30109QDG 64 pin TQFP
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
-40°C to +85°C
• Simple hardware control interface
• Accepts two input references and synchronizes to
any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz, 19.44 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Holdover frequency accuracy of 1.5 x 10-7
• Less than 24 psrms intrinsic jitter on the
19.44 MHz output clock, compliant with OC-3 and
STM-1 jitter specifications
• Less than 0.6 nspp intrinsic jitter on all output
clocks
• External master clock source: clock oscillator or
crystal
Applications
• Synchronization and timing control for DSLAM,
Gateway and PBX systems that require Stratum
4/4E timing
• Lock, Holdover and selectable Out of Range
indication
• Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
• Line Card synchronization for SDH/PDH
applications
• Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
REF0
REF1
REF_FAIL0
REF_FAIL1
OOR_SEL
REF_SEL
RST
OSCi OSCo TIE_CLR
BW_SEL LOCK OUT_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Feedback Frequency
Select
MUX
DS1
Synthesizer
SONET/SDH
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C19o
F2ko
TRST
MODE_SEL1:0 HMS HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL30109
Data Sheet
F4/F65o
F16o
AGND
IC
REF_SEL
NC
REF0
NC
REF1
NC
IC
OOR_SEL
VDD
NC
TIE_CLR
BW_SEL
48 46 44 42 40 38 36 34
32
50
30
52
28
54
56 ZL30109
26
24
58
22
60
20
62
18
64
2 4 6 8 10 12 14 16
C1.5o
NC
NC
AVDD
IC
IC
OUT_SEL
VDD
NC
GND
IC
OSCi
OSCo
RST
MODE_SEL1
MODE_SEL0
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1)
Note 1: The ZL30109 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30109
does not use the e-Pad TQFP.
5
Zarlink Semiconductor Inc.
5 Page 
ZL30109
SCM or CFM failure
Data Sheet
current REF
timer
REF_FAIL
2.5 s
10 s
HOLDOVER
Figure 4 - Behaviour of the Dis/Re-qualify Timer
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the
REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the
mode (Holdover/Normal) of the DPLL.
C20 Clock Accuracy
0 ppm
C20
-83 -64
0 64 83
Out of Range
In Range
+32 ppm
-32 ppm
C20
-51 -32 0 32
96 115
C20
-115 -96 -32 0 32 51
Out of Range
In Range
Out of Range
In Range
-200 -150 -100 -50
0 50 100 150 200
Frequency offset [ppm]
C20: 20 MHz master clock on OSCi
Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0)
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet ZL30109.PDF ] | |
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