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PDF EPCS16 Data sheet ( Hoja de datos )

Número de pieza EPCS16
Descripción (EPCS1 - EPCS64) Serial Configuration Devices
Fabricantes Altera Corporation 
Logotipo Altera Corporation Logotipo



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C51014-2.0
Features
Functional
Description
Chapter 4. Serial Configuration
Devices (EPCS1, EPCS4,
EPCS16 & EPCS64) Data Sheet
The serial configuration devices provide the following features:
1-, 4-, 16-, and 64-Mbit flash memory devices that serially configure
Stratix® II FPGAs and the Cyclone™ series FPGAs using the active
serial (AS) configuration scheme
Easy-to-use four-pin interface
Low cost, low pin count and non-volatile memory
Low current during configuration and near-zero standby mode
current
3.3-V operation
Available in 8-pin and 16-pin small outline integrated circuit (SOIC)
package
Enables the Nios® processor to access unused flash memory through
AS memory interface
Re-programmable memory with more than 100,000 erase/program
cycles
Write protection support for memory sectors using status register
bits
In-system programming support with SRunner software driver
Programming support with USB Blaster™ or ByteBlaster™ II
download cables
Additional programming support with the Altera® Programming
Unit (APU) and programming hardware from BP Microsystems,
System General, and other vendors
Software design support with the Altera Quartus® II development
system for Windows-based PCs as well as Sun SPARC station and
HP 9000 Series 700/800
Delivered with the memory array erased (all the bits set to 1)
1 Whenever the term “serial configuration device(s)” is used in
this document, it refers to Altera EPCS1, EPCS4, EPCS16, and
EPCS64 devices.
With SRAM-based devices such as Stratix II FPGAs and the Cyclone
series FPGAs, configuration data must be reloaded each time the device
powers up, the system initializes, or when new configuration data is
needed. Serial configuration devices are flash memory devices with a
Altera Corporation
July 2004
Core Version a.b.c variable
4–1
Preliminary

1 page




EPCS16 pdf
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
f
Accessing Memory in Serial Configuration Devices
You can access the unused memory locations of the serial configuration
device to store or retrieve data through the Nios processor and SOPC
Builder. SOPC Builder is an Altera tool for creating bus-based (especially
microprocessor-based) systems in Altera devices. SOPC Builder
assembles library components like processors and memories into custom
microprocessor systems.
SOPC Builder includes the active serial memory interface (ASMI)
peripheral, an interface core specifically designed to work with the serial
configuration device. Using this core, you can create a system with a Nios
embedded processor that allows software access to any memory location
within the serial configuration device.
For more information on accessing memory within the serial
configuration device, see the Active Serial Memory Interface Data Sheet.
Active Serial
FPGA
Configuration
Stratix II FPGAs and the Cyclone series FPGAs can be configured with a
serial configuration device through the AS configuration mode.
1 This section is only relevant for FPGAs that support the Active
Serial (AS) configuration scheme. Only Stratix II FPGAs and the
Cyclone series FPGAs support the AS configuration scheme.
There are four signals on the serial configuration device that interface
directly with the FPGA’s control signals. The serial configuration device
signals DATA, DCLK, ASDI, and nCS interface with DATA0, DCLK, ASDO,
and nCSO control signals on the FPGA, respectively. Figure 4–2 shows a
serial configuration device programmed via a download cable which
configures an FPGA in AS mode. Figure 4–3 shows a serial configuration
device programmed using the APU or a third-party programmer
configuring an FPGA in AS configuration mode.
Altera Corporation
July 2004
Core Version a.b.c variable
4–5
Configuration Handbook, Volume 2

5 Page





EPCS16 arduino
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
All attempts to access the memory contents while a write or erase cycle is
in progress will not be granted, and the write or erase cycle will continue
unaffected.
Table 4–8. Operation Codes for Serial Configuration Devices
Operation Operation Code (1) Address Bytes Dummy Bytes
Write enable
Write disable
Read status
Read bytes
Read silicon ID
Write status
Write bytes
Erase bulk
Erase sector
0000 0110
0000 0100
0000 0101
0000 0011
1010 1011
0000 0001
0000 0010
1100 0111
1101 1000
0
0
0
3
0
0
3
0
3
0
0
0
0
3
0
0
0
0
Data Bytes
0
0
1 to infinite (2)
1 to infinite (2)
1 to infinite (2)
1
1 to 256 (3)
0
0
DCLK fMAX
(MHz)
25
25
25
20
25
25
25
25
25
Notes to Table 4–8:
(1) The MSB is listed first and the least significant bit (LSB) is listed last.
(2) The status register, data or silicon ID are read out at least once on the DATA pin and will continuously be read out
until nCS is driven high
(3) Write bytes operation requires at least one data byte on the DATA pin. If more than 256 bytes are sent to the device,
only the last 256 bytes are written to the memory.
Write Enable Operation
The write enable operation code is b'0000 0110, and the most
significant bit is listed first. The write enable operation sets the write
enable latch bit, which is bit 1 in the status register. Always set the write
enable latch bit before write bytes, write status, erase bulk, and erase
sector operations. Figure 4–5 shows the timing diagram for the write
enable operation. Figures 4–7 and 4–8 show the status register bit
definitions.
Altera Corporation
July 2004
Core Version a.b.c variable
4–11
Configuration Handbook, Volume 2

11 Page







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