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PDF GS88136T Data sheet ( Hoja de datos )
| Número de pieza | GS88136T | |
| Descripción | (GS88118 / GS88136T) Sync Burst SRAMs | |
| Fabricantes | GSI | |
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100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
GS88118/36T-11/11.5/100/80/66
512K x 18, 256K x 36 ByteSafe™ 100 MHz–66 MHz
8Mb Sync Burst SRAMs
3.3 V VDD
3.3 V and 2.5 V I/O
1.11 9/2000Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) Operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 100-lead TQFP package
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
tKQ
IDD
tKQ
tCycle
IDD
-11
10 ns
4.0 ns
225 mA
11 ns
15 ns
180 mA
-11.5
10 ns
4.0 ns
225 mA
11.5 ns
15 ns
180 mA
-100
10 ns
4.0 ns
225 mA
12 ns
15 ns
180 mA
-80
12.5 ns
4.5 ns
200 mA
14 ns
15 ns
175 mA
-66
15 ns
5.0 ns
185 mA
18 ns
20 ns
165 mA
Functional Description
Applications
The GS88118//36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118//36T is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
ByteSafe™ Parity Functions
The GS88118/36T features ByteSafe data security functions.
See detailed discussion following.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118//36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
Rev: 1.11 9/2000
1/33 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1 page  
Pin Location
64
14
31
38
39
42
43
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
Symbol
ZZ
FT
LBO
TMS
TDI
TDO
TCK
VDD
VSS
VDDQ
Typ
e
I
I
I
I
I
O
I
I
I
I
Preliminary
GS88118/36T-11/11.5/100/80/66
Description
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.11 9/2000
5/33 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5 Page 
Preliminary
GS88118/36T-11/11.5/100/80/66
Simplified State Diagram with G
X
Deselect
WR
WR
X
First Write
CW
R
CR
W First Read X
CW CR
W
X
R
Burst Write
CR
CW
R
W Burst Read X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.11 9/2000
11/33
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GS88136T.PDF ] | |
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