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PDF FAN4800 Data sheet ( Hoja de datos )

Número de pieza FAN4800
Descripción Low Start-Up Current PFC/PWM Controller Combos
Fabricantes Fairchild Semiconductor 
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No Preview Available ! FAN4800 Hoja de datos, Descripción, Manual

November 2010
FAN4800
Low Startup Current PFC/PWM Controller Combinations
Features
„ Low Startup Current (100µA Typical)
„ Low Operating Current (2.5mA Typical)
„ Low Total Harmonic Distortion, High Power Factor
„ Pin-Compatible Upgrade for the ML4800
„ Average Current, Continuous or Discontinuous Boost,
Leading-Edge PFC
„ Slew Rate Enhanced Transconductance Error
Amplifier for Ultra-Fast PFC Response
„ Internally Synchronized Leading-Edge PFC and
Trailing-Edge PWM
„ Reduction of Ripple Current in the Storage Capacitor
between the PFC and PWM Sections
„ PWM Configurable for Current Mode or Voltage Mode
„ Additional Folded-Back Current Limit for PWM Section
„ 20V BiCMOS Process
„ VIN OK Guaranteed Turn-on PWM at 2.25V
„ VCC OVP Comparator, Low-Power Detect Comparator
„ Current-Fed Gain Modulator for Improved Noise
Immunity
„ Brownout Control, Over-Voltage Protection, UVLO,
Soft-Start, and Reference OK
„ Available in16-DIP Package
Applications
„ Desktop PC Power Supply
„ Internet Server Power Supply
„ Uninterruptible Power Supply (UPS)
„ Battery Charger
„ DC Motor Power Supply
„ Monitor Power Supply
„ Telecom System Power Supply
„ Distributed Power
Description
The FAN4800 is a controller for power-factor-corrected,
switched-mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower-cost bulk capaci-
tors, reduces power line loading and stress on the
switching FETs, and results in a power supply that fully
complies with IEC-1000-3-2 specifications. Intended as a
BiCMOS version of the industry-standard ML4800, the
FAN4800 includes circuits for the implementation of
leading-edge, average-current, boost-type power factor
correction and a trailing-edge Pulse Width Modulator
(PWM). A gate driver with 1A capabilities minimizes the
need for external driver circuits. Low-power require-
ments improve efficiency and reduce component costs.
An over-voltage comparator shuts down the PFC section
in the event of a sudden decrease in load. The PFC sec-
tion also includes peak current limiting and input voltage
brownout protection. The PWM section can be operated
in current or voltage mode, at up to 250kHz, and
includes an accurate 50% duty cycle limit to prevent
transformer saturation.
The FAN4800 includes a folded-back current limit for the
PWM section to provide short-circuit protection.
16-PDIP
Ordering Information
Part Number
FAN4800IN
FAN4800IN_G
Operating
Temperature Range
-40°C to +125°C
-40°C to +125°C
Package
16-PDIP
16-PDIP
Packing
Method
Rail
Rail
Marking
Code
FAN4800
FAN4800
© 2005 Fairchild Semiconductor Corporation
FAN4800 Rev. 1.0.6
www.fairchildsemi.com

1 page




FAN4800 pdf
Electrical Characteristics
Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3KΩ, CT = 470pF, and TA = -40°C to 125°C.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
VOLTAGE ERROR AMPLIFIER
VFB Input Voltage Range(1)
gm1 Transconductance
0 6V
50 70 90 µmho
Vref(PFC)
Ib(VEAO)
VEAO(H)
VEAO(L)
Feedback Reference Voltage
Input Bias Current(2)
Output High-Voltage
Output Low-Voltage
Isink(V) Sink Current
Isource(V) Source Current
GV
PSRR1
Open-Loop Gain(1)(3)
Power Supply Rejection Ratio(1)
CURRENT ERROR AMPLIFIER
VIEAO Input Voltage Range(1)
gm2 Transconductance
TA = 25°C
TA = 25°C, VFB = 3V,
VEAO = 6.0V
TA = 25°C, VFB = 1.5V
VEAO = 1.5V
11V < VCC < 16.5V
2.45
-1.00
5.8
2.50
-0.05
6.0
0.1
2.55
0.4
-35 -20
V
mA
V
V
µA
30 40
50 60
50 60
µA
dB
dB
-1.5 0.7 V
50 85 100 µmho
Voffset
Ibeao
IEAO(H)
IEAO(L)
Isink(I)
Isource(I)
Gi
PSRR2
Input Offset Voltage
Input Bias Current(1)
Output High-Voltage
Output Low-Voltage
Sink Current
Source Current
Open-Loop Gain(1)
Power Supply Rejection Ratio(1)
PFC OVP COMPARATOR
TA = 25°C
ISENSE = +0.5, IEAO = 4.0V
ISENSE = -0.5, IEAO = 1.5V
11V < VCC < 16.5V
-1
4.00 4.25
1.0
-65
35 75
60 70
60 75
25
1.2
-35
mV
µA
V
V
µA
µA
dB
dB
Vovp Threshold Voltage
HY(ovp) Hysteresis
LOW-POWER DETECT COMPARATOR
TA = 25°C
TA = 25°C
2.70 2.78 2.90
230 350
V
mV
Vth(lp) Threshold Voltage
VCC OVP COMPARATOR
TA = 25°C
0.15 0.30 0.40 V
VCC_OVP Threshold Voltage
HY(VCC_OVP) Hysteresis
TRI-FAULT DETECT
TA = 25°C
TA = 25°C
17.5 17.9 18.5
1.40 1.50 1.65
V
V
td(F) Time to Fault Detect HIGH(1)
VFB = VFault Detect LOW to
VFB = Open. 470pF from VFB
to GND
2 4 ms
F(L) Fault Detect LOW
0.4 0.5 0.6 V
© 2005 Fairchild Semiconductor Corporation
FAN4800 Rev. 1.0.6
5
www.fairchildsemi.com

5 Page





FAN4800 arduino
16
VEAO
15 VFB
2.5V
0.3V
2 IAC
4 VRMS
3 ISENSE
GAIN
MODULATOR
1
IEAO
Low Power
Detector
3.5k
POWER FACTOR CORRECTOR
VCC
17.9V
VCC OVP
2.78V
TRI-FAULT
PFC OVP
0.5V
-1V
3.5k PFC CMP
PFC ILIMIT
13
VCC
7.5V
REFERENCE
VREF 14
SQ
R
SQ
R
PFC OUT
12
RAMP1
7
OSCILLATOR
CLK
FAN4800 Rev.02
Figure 7. PFC Section Block Diagram
1.6 Error Amplifier Compensation
The voltage loop gain(s) is given by:
The PWM loading of the PFC can be modeled as a neg-
ative resistor because an increase in the input voltage to
the PWM causes a decrease in the input current. This
response dictates the proper compensation of the two
transconductance error amplifiers.
Figure 8 shows the types of compensation networks
most commonly used for the voltage and current error
amplifiers, along with their respective return points. The
current-loop compensation is returned to VREF to pro-
duce a soft-start characteristic on the PFC: As the refer-
ence voltage increases from 0V, it creates a
differentiated voltage on IEAO, which prevents the PFC
from immediately demanding a full duty cycle on its
boost converter.
=
ΔVOUT
ΔVEAO
×
ΔVFB
ΔVOUT
×
ΔVEAO
ΔVFB
PIN × 2.5V
V
2
OUTDC
×
ΔVEAO
×S
× CDC
× GMV
× ZC
(6)
where:
ZC: Compensation network for the voltage loop.
GMV:
Transconductance of VEAO.
PIN: Average PFC input power.
V2OUTDC: PFC boost output voltage (typical designed
value is 380V).
1.7 PFC Voltage Loop
CDC:
PFC boost output capacitor.
There are two major concerns when compensating the
voltage loop error amplifier (VEAO); stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency half that of the line fre-
quency, or 23Hz for a 47Hz line (lowest anticipated inter-
national power frequency). The gain vs. input voltage of
the FAN4800’s voltage error amplifier (VEAO) has a spe-
cially shaped non-linearity, so that under steady-state
operating conditions, the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line
or load conditions causes the input to the voltage error
amplifier (VFB) to deviate from its 2.5V (nominal) value. If
this happens, the transconductance of the voltage error
amplifier increases significantly, as shown in the Figure
4. This raises the gain-bandwidth product of the voltage
loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with
conventional linear gain characteristics.
1.8 PFC Current Loop
The compensation of the current amplifier (IEAO) is simi-
lar to that of the voltage error amplifier (VEAO) with the
exception of the choice of crossover frequency. The
crossover frequency of the current amplifier should be at
least ten times that of the voltage amplifier to prevent
interaction with the voltage loop. It should also be limited
to less than one sixth of the switching frequency, e.g.,
16.7kHz for a 100kHz switching frequency.
The current loop gain(s) is given by:
=
ΔVISENSE
ΔDOFF
×
ΔDOFF
ΔIEAO
×
ΔIEAO
ΔVISENSE
VOUTDC × RS
S × L × 2.5V
× GMI
× ZCI
(7)
© 2005 Fairchild Semiconductor Corporation
FAN4800 Rev. 1.0.6
11
www.fairchildsemi.com

11 Page







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