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PDF FAN5026 Data sheet ( Hoja de datos )

Número de pieza FAN5026
Descripción Dual DDR/Dual-output PWM Controller
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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October 2005
FAN5026
Dual DDR/Dual-Output PWM Controller
Features
Highly flexible dual synchronous switching PWM
controller includes modes for:
– DDR mode with in-phase operation for reduced
channel interference
– 90° phase shifted two-stage DDR Mode for reduced
input ripple
– Dual Independent regulators 180° phase shifted
Complete DDR Memory power solution
– VTT Tracks VDDQ/2
– VDDQ/2 Buffered Reference Output
Lossless current sensing on low-side MOSFET or
Precision current sensing using sense resistor
VCC Under-voltage Lockout
Wide power input range: 3 to 16V
Excellent dynamic response with Voltage
Feed-Forward and Average Current Mode control
Power-Good Signal
Supports DDR-II and HSTL
TSSOP28 package
Applications
DDR VDDQ and VTT voltage generation
Desktop computer
Graphics cards
General Description
The FAN5026 PWM controller provides high efficiency
and regulation for two output voltages adjustable in the
range from 0.9V to 5.5V that are required to power I/O,
chip-sets, and memory banks in high-performance com-
puters, set top boxes, and VGA cards. Synchronous rec-
tification contributes to high efficiency over a wide range
of loads. Efficiency is even further enhanced by using
MOSFET’s RDS(ON) as a current sense component.
Feed-forward ramp modulation, average current mode
control scheme, and internal feedback compensation
provide fast response to load transients. Out-of-phase
operation with 180° phase shift reduces input current
ripple. The controller can be transformed into a com-
plete DDR memory power supply solution by activating a
designated pin. In DDR mode of operation one of the
channels tracks the output voltage of another channel
and provides output current sink and source capability —
features essential for proper powering of DDR chips. The
buffered reference voltage required by this type of mem-
ory is also provided. The FAN5026 monitors these out-
puts and generates separate PGx (power good) signals
when the soft-start is completed and the output is within
±10% of its set point. A built-in over-voltage protection
prevents the output voltage from going above 120% of
the set point. Normal operation is automatically restored
when the over-voltage conditions go away. Under-volt-
age protection latches the chip off when either output
drops below 75% of its set value after the soft-start
sequence for this output is completed. An adjustable
over-current function monitors the output current by
sensing the voltage drop across the lower MOSFET. If
precision current-sensing is required, an external cur-
rent-sense resistor may optionally be used.
Ordering Information
Part Number
FAN5026MTC
FAN5026MTCX
Temperature Range
-40°C to 85°C
-40°C to 85°C
Package
TSSOP-28
TSSOP-28
Packing
Rails
Tape and Reel
©2005 Fairchild Semiconductor Corporation
FAN5026 Rev. 1.0.5
1
www.fairchildsemi.com

1 page




FAN5026 pdf
Electrical Specifications Recommended operating conditions, unless otherwise noted.
Parameter
Conditions
Power Supplies
VCC Current
LDRV, HDRV Open, VSEN forced
above regulation point
Shut-down (EN=0)
VIN Current – Sinking
VIN = 15V
VIN Current – Sourcing
VIN = 0V
VIN Current – Shut-down
UVLO Threshold
Rising VCC
Falling
UVLO Hysteresis
Oscillator
Frequency
Ramp Amplitude, pk–pk
VIN = 16V
Ramp Amplitude, pk–pk
VIN = 5V
Ramp Offset
Ramp / VIN Gain
VIN 3V
Ramp / VIN Gain
1V < VIN < 3V
Reference and Soft Start
Internal Reference Voltage
Soft Start Current (ISS)
Soft Start Complete Threshold
at start-up
PWM Converters
Load Regulation
IOUTX from 0 to 5A,
VIN from 5 to 15V
VSEN Bias Current
Under-Voltage Shutdown
as % of set point. 2µS noise filter
Over-Voltage Threshold
as % of set point. 2µS noise filter
ISNS Over-Current Threshold
Minimum Duty Cycle
RILIM= 68.5Ksee Figure 10.
Output Drivers
HDRV Output Resistance
Sourcing
Sinking
LDRV Output Resistance
Sourcing
Sinking
PG (Power Good Output) and Control pins
Lower Threshold
as % of set point, 2µS noise filter
Upper Threshold
as % of set point, 2µS noise filter
PG Output Low
IPG = 4mA
Leakage Current
PG2/REF2OUT Voltage
DDR, EN Inputs
VPULLUP = 5V
DDR = 1, 0 mA < IREF2OUT < 10mA
Input High
Input Low
Min. Typ. Max.
2.2 3.0
30
10 30
–15 –30
1
4.3 4.55 4.75
4.1 4.25 4.45
300
255 300 345
2
1.25
0.5
125
250
0.891 0.9 0.909
–5
1.5
-2 +2
50 80 120
70 75 80
115 120 125
112 140 168
10
12 15
2.4 4
12 15
1.2 2
–86 –94
108 116
0.5
1
99 1.01
2
0.8
Units
mA
µA
µA
µA
µA
V
V
mV
KHz
V
V
V
mV/V
mV/V
V
µA
V
%
nA
%
%
µA
%
%
%
V
µA
% VREF2
V
V
FAN5026 Rev. 1.0.5
5
www.fairchildsemi.com

5 Page





FAN5026 arduino
Setting the Current Limit
A ratio of ISNS is also compared to the current
established when a 0.9 V internal reference drives the
ILIM pin. The threshold is determined at the point when
the I---S---9-N-----S-- > I---L---I--M--3-----×-----4- . Since
ISNS = -I-L--1-O--0--A--0--D--+---×--R--R---S--D-E---S-N--(--SO---E-N----) therefore,
ILIMIT
=
--0---.--9---V----
RILIM
×
43--
×
9-----×-----(---1---0---0-----+-----R-----S---E----N---S----E----)
RDS(ON)
or
RILIM = -I-1L---I-0-M--.--8I--T- × -(--1---0----0-R---+-D----SR---(--SO---E-N---N-)---S---E----)
(3a)
(3b)
Since the tolerance on the current limit is largely depen-
dent on the ratio of the external resistors, it is fairly accu-
rate if the voltage drop on the Switching Node side of
RSENSE is an accurate representation of the load current.
When using the MOSFET as the sensing element, the
variation of RDS(ON) causes proportional variation in the
ISNS. This value not only varies from device to device,
but also has a typical junction temperature coefficient of
about 0.4%/°C (consult the MOSFET datasheet for
actual values), so the actual current limit set point will
decrease proportional to increasing MOSFET die tem-
perature. A factor of 1.6 in the current limit setpoint
should compensate for all MOSFET RDS(ON) variations,
assuming the MOSFET’s heat sinking will keep its oper-
ating die temperature below 125°C.
LDRV
ISNS RSENSE
Q2
PGND
Figure 11. Improving Current Sensing Accuracy
More accurate sensing can be achieved by using a resis-
tor (R1) instead of the RDS(ON) of the FET as shown in
Figure 11. This approach causes higher losses, but
yields greater accuracy in both VDROOP and ILIMIT. R1 is
a low value (e.g. 10m) resistor.
Current limit (ILIMIT) should be set sufficiently high as to
allow inductor current to rise in response to an output
load transient. Typically, a factor of 1.3 is sufficient. In
addition, since ILIMIT is a peak current cut-off value, we
will need to multiply ILOAD(MAX) by the inductor ripple cur-
rent (we'll use 25%). For example, in Figure 5 the target
for ILIMIT would be:
ILIMIT > 1.2 × 1.25 × 1.6 × 6A 14A
(4)
Gate Driver Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
providing necessary amplification, level shifting and
shoot-through protection. Also, it has functions that help
optimize the IC performance over a wide range of oper-
ating conditions. Since MOSFET switching time can vary
dramatically from type to type and with the input voltage,
the gate control logic provides adaptive dead time by
monitoring the gate-to-source voltages of both upper and
lower MOSFETs. The lower MOSFET drive is not turned
on until the gate-to-source voltage of the upper MOSFET
has decreased to less than approximately 1 volt. Simi-
larly, the upper MOSFET is not turned on until the gate-
to-source voltage of the lower MOSFET has decreased
to less than approximately 1 volt. This allows a wide vari-
ety of upper and lower MOSFETs to be used without a
concern for simultaneous conduction, or shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to work properly. Any delay
along that path will subtract from the delay generated by
the adaptive dead-time circuit and shoot-through may
occur.
Frequency Loop Compensation
Due to the implemented current mode control, the modu-
lator has a single pole response with -1 slope at fre-
quency determined by load
FPO = 2----π----R---1-O----C-----O--
(5)
where RO is load resistance and CO is load capacitance.
For this type of modulator, Type 2 compensation circuit is
usually sufficient. To reduce the number of external com-
ponents and simplify the design task, the PWM controller
has an internally compensated error amplifier. Figure 12
shows a Type 2 amplifier and its response along with the
responses of a current mode modulator and of the con-
verter. The Type 2 amplifier, in addition to the pole at the
origin, has a zero-pole pair that causes a flat gain region
at frequencies between the zero and the pole.
FZ = -2---π----R--1--2---C-----1- = 6kHz
(6a)
FP = -2---π----R--1--2---C-----2- = 600kHz
(6b)
This region is also associated with phase ‘bump’ or
reduced phase shift. The amount of phase shift reduction
depends the width of the region of flat gain and has a
maximum value of 90 degrees. To further simplify the
converter compensation, the modulator gain is kept inde-
pendent of the input voltage variation by providing feed-
forward of VIN to the oscillator ramp.
FAN5026 Rev. 1.0.5
11
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