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PDF K4C89323AF Data sheet ( Hoja de datos )
| Número de pieza | K4C89323AF | |
| Descripción | DOUBLE DATA RATE Network-DRAM | |
| Fabricantes | Samsung semiconductor | |
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K4C89363AF
Network-DRAM-II Specification
Version 0.0
- 1 - REV. 0.0 Nov. 2002
1 page  
K4C89363AF
Block Diagram
CLK
CLK
PD
DLL
CLOCK
BUFFER
CS C O M M A N D
FN D E C O D E R
A0 ~ A14
BA0, BA1
ADDRESS
BUFFER
REFRESH
COUNTER
To Each Block
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
BANK #3
BANK #2
BANK #1
BANK #0
MEMORY
CELL
ARRAY
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
COLUMN DECODER
BURST
COUNTER
WRITE ADDRESS
LATCH
ADDRESS
COMPARATOR
DS
QS
READ
DATA
BUFFER
WRITE
DATA
BUFFER
DQ BUFFER
DQ0 ~ DQ35
Note : The K4C89363AD configuration is 4 Bank of 16384 x 128 x 36 of cell array with the DQ pins numbered DQ0~DQ35.
- 5 - REV. 0.0 Nov. 2002
5 Page 
K4C89363AF
AC Test Conditions
Symbol
V IH ( m i n )
VIL (max)
V REF
V TT
V SWING
VR
V ID ( A C )
SLEW
V OTR
Parameter
Input high voltage (minimum)
Input low voltage (maximum)
Input reference voltage
Termination voltage
Input signal peak to peak swing
Differential clock input reference level
Input differential voltage
Input signal minimum slew rate
Output timing measurement reference voltage
VddQ
Value
VREF + 0.2
VREF - 0.2
VddQ/2
VREF
0.7
VX(AC)
1.0
2.5
VddQ/2
V SWING
V IH min (AC)
VREF
Output
V IL m a x (AC)
25 Ω
Vss
∆T
∆T
Units
V
V
V
V
V
V
V
V/ns
V
Z=50Ω
Z=50Ω
Notes
9
V TT
50 Ω
50 Ω
V TT
S l e w = (V IH m i n ( A C ) - V ILm a x ( A C ) ) /∆ T
AC Test Load
N o t e s : 1 . T r a n s i t i o n t i m e s a r e m e a s u r e d b e t w e e n V I H m i n ( D C ) a n d V IL m a x (DC).
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to tCK contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and C LK) AC cross point.
4. These parameters are measured from signal transition point of D S crossing V REF level.
5. The t REFI(MAX.) applies to equally distributed refresh method.
The t REFI(MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength.
- 11 -
REV. 0.0 Nov. 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K4C89323AF.PDF ] | |
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