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PDF K4C89093AF Data sheet ( Hoja de datos )

Número de pieza K4C89093AF
Descripción 288Mb x18 Network-DRAM2 Specification
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K4C89093AF Hoja de datos, Descripción, Manual

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K4C89183AF
288Mb x18 Network-DRAM2 Specification
Version 0.7
- 1 - REV. 0.7 Jan. 2005

1 page




K4C89093AF pdf
K4C89183AF
Pin Names
Pin
A0 ~ A14
BA0, BA1
DQ0 ~ DQ17
CS
FN
PD
CLK, CLK
DS/QS
VDD
VSS
VDDQ
VSSQ
VREF
NC
Name
Address Input
Bank Address
Data Input/Output
Chip Select
Function Control
Power Down Control
Clock Input
Write/Read data strobe
Power (+2.5V)
Ground
Power (+1.8V)
(for I/O buffer)
Ground
(for I/O buffer)
Reference Voltage
No Connection
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
x18
123456
Index
A Vss DQ17
B DQ16 VssQ
C DQ15 VDDQ
D DQ14 DQ13
DQ0 VDD
VDDQ DQ1
VssQ DQ2
DQ4 DQ3
E DQ12 VssQ
F DQ11 VDDQ
G DQ10 VssQ
H DQ9 DS
VDDQ DQ5
VssQ DQ6
VDDQ DQ7
QS DQ8
J
VREF
Vss
K CLK CLK
VDD A14
FN A13
L A12 PD
CS NC
M A11 A9
BA1 BA0
N A8 A7
A0 A10
P A5 A6
A2 A1
R VSS A4
A3 VDD
- 5 - REV. 0.7 Jan. 2005

5 Page





K4C89093AF arduino
K4C89183AF
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
Parameter
F6
Min Max
FB
Min Max
F5
Units Notes
Min Max
tRC Random Cycle Time
20.0 - 22.5 - 25 -
3
tCK Clock Cycle Time
CL = 4
4.0
6.0
4.5
6.0
5.0
6.0
CL = 5 3.33 6.0 3.75 6.0 4.5 6.0
CL = 6
3.0
6.0 3.33 6.0
4.0
6.0
3
3
3
tRAC
Random Access Time
- 20.0 - 22.5 -
25
3
tCH Clock High Time
0.45*tCK - 0.45*tCK - 0.45*tCK -
3
tCL Clock Low Time
0.45*tCK - 0.45*tCK - 0.45*tCK -
3
tCKQS
QS Access Time from CLK
-0.45
0.45
-0.45
0.45
-0.5
0.5
3, 8
tQSQ
Data Output Skew from QS
- 0.2 - 0.25 - 0.3
4
tAC Data Access Time from CLK
-0.5 0.5 -0.5 0.5 -0.6 0.6
3, 8
tOH Data Output Hold Time from CLK
-0.5 0.5 -0.5 0.5 -0.6 0.6
3, 8
tHP CLK half period ( minium of Actual tCH, tCL)
min(tCH,
tCL)
-
min(tCH,
tCL)
-
min(tCH,
tCL)
-
3
tQSP
QS(Read) Pulse Width
tHP-tQHS - tHP-tQHS - tHP-tQHS -
4, 8
tQSQV
Data Output Valid Time from QS
tHP-tQHS - tHP-tQHS - tHP-tQHS -
4, 8
tQHS
DQ, QS Hold skew factor
0.055x
0.055x
0.055x
- tCK+0.17 - tCK+0.17 - tCK+0.17
tDQSS
tDSPRE
DS(Write) Low to High Setup Time
DS(Write) Preamble Pulse Width
0.8*tCK
0.4*tCK
1.2*tCK
-
0.8*tCK
0.4*tCK
1.2*tCK
-
0.8*tCK
0.4*tCK
1.2*tCK
-
ns
3
4
tDSPRES DS First Input Setup Time
0-0-0-
3
tDSPREH DS First Low Input Hold Time
0.3*tCK - 0.3*tCK - 0.3*tCK -
3
tDSP
DS High or Low Input Pulse Width
0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK
4
CL = 4 0.75
-
0.8
-
1.0
-
tDSS
DS Input Falling Edge to Clock Setup
Time
CL = 5
CL = 6
0.75
0.75
-
-
0.8
0.8
-
-
1.0
1.0
-
-
3, 4
3, 4
3, 4
CL = 7
-
-
-
-
-
-
3, 4
tDSPST DS(Write) Postamble Pulse Width
0.45*tCK - 0.45*tCK
0.45*tCK
-
4
tDSPSTH DS(Write) Postamble Hold Time
CL = 4 0.75
-
0.8
-
1.0
-
CL = 5 0.75
-
0.8
-
1.0
-
CL = 6 0.75
-
0.8
-
1.0
3, 4
3, 4
3, 4
CL = 7
-
-
-
-
-
-
3, 4
tDS Data Input Setup Time from DS
0.3 - 0.35 - 0.4 -
4
tDH Data Input Hold Time from DS
0.3 - 0.35 - 0.4 -
4
tIS Command / Address Input Setup Time
0.6 - 0.6 - 0.7 -
3
tIH Command / Address Input Hold Time
0.6 - 0.6 - 0.7 -
3
- 11 - REV. 0.7 Jan. 2005

11 Page







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