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PDF KM641001B Data sheet ( Hoja de datos )

Número de pieza KM641001B
Descripción CMOS SRAM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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No Preview Available ! KM641001B Hoja de datos, Descripción, Manual

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PRELIMINARY
KM641001B/BL
CMOS SRAM
Document Title
256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out.
Revision History
Rev.No.
Rev. 0.0
Rev.1.0
Rev. 2.0
Rev.3.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete 17ns, L-version and Industrial Temperature Part.
2.3. Delete VOH1=3.95V.
2.4. Delete Data Retention Characteristics and Wave form.
2.5. Relex operating current.
Speed
Previous
Now
15ns
120mA
120mA
17ns
110mA
-
20ns
100mA
118mA
3.1. Add Low power Version.
3.2. Add Data Retention chcracteristics.
Draft Data
Feb. 1st 1997
Jun. 1st 1997
Remark
Design Target
Preliminary
Feb. 6th 1998 Final
Jul. 28th 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev. 3.0
July 1998

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KM641001B pdf
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KM641001B/BL
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
KM641001B/BL-15
Min Max
15 -
10 -
0-
10 -
10 -
15 -
0-
08
7-
0-
3-
PRELIMINARY
CMOS SRAM
KM641001B/BL-20
Min Max
20 -
12 -
0-
12 -
12 -
20 -
0-
0 10
9-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tRC
tOH
Previous Valid Data
tAA
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
Current
ICC
ISB
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tRC
tHZ(3,4,5)
tOHZ
Valid Data
tOH
tPD
50%
-5-
Rev. 3.0
July 1998

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