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PDF IR3084 Data sheet ( Hoja de datos )
| Número de pieza | IR3084 | |
| Descripción | XPHASETM VR 10/11 CONTROL IC | |
| Fabricantes | International Rectifier | |
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IR3084
Data Sheet No. PD94718
XPHASETM VR 10/11 CONTROL IC
DESCRIPTION
The IR3084 Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible
way to implement a complete VR10 or VR11 power solution. The “Control” IC provides overall system
control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a
multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES
• 1 to X phase operation with matching Phase IC
• Supports both VR11 8-bit VID code and extended VR10 7-bit VID code
• 0.5% Overall System Setpoint Accuracy
• VID Select pin sets the DAC to either VR10 or VR11
• VID Select pin selects either VR11 or legacy VR10 type startups
• Programmable VID offset and Load Line output impedance
• Programmable VID offset function at the Error Amp’s non-inverting input allowing zero offset
• Programmable Dynamic VID Slew Rate
• ±300mV Differential Remote Sense
• Programmable 150kHz to 1MHz oscillator
• Enable Input with 0.85V threshold and 100mV of hysteresis
• VR Ready output provides indication of proper operation and avoids false triggering
• Phase IC Gate Driver Bias Regulator / VRHOT Comparator
• Operates from 12V input with 9.9V Under-Voltage Lockout
• 6.9V/6mA Bias Regulator provides System Reference Voltage
• Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
• Small thermally enhanced 5mm x 5mm, 28 pin MLPQ package
TYPICAL APPLICATION CIRCUIT
VCC_SENSE
VSS_SENSE
RT2 R117
4.7K, B=4450 1.21K
RFB1
162
CFB
10nF
C1009
100pF
RFB
324
CCP1
100pF
RCP
2.49K
CCP
56nF
+5.0V
R137
2K
18
17
FB
EAOUT VRRDY 27
IIN 15
RMPOUT 19
RDRP
787
VBIAS 20
IR3084MTR
C134
0.1uF
EA
VREG_12V_FILTERED
VR_RDY
ISHARE
RMP
VBIAS
C89
100pF
R1331 Q4
1 CJD200
C204
0.1uF
OUTEN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID_SEL
VREG_12V_FILTERED
R30
10
C130
0.1uF
16
28
9
8
7
6
5
4
3
2
1
21
26
CSS/DEL
0.1uF
VDRP
ENABLE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VIDSEL
VCC
SS/DEL
REGDRV
REGFB
REGSET
VSETPT
OCSET
VDAC
ROSC
VOSNS-- LGND
24
23
25
RVSETPT
124
14
ROCSET
13
15.8K
12
ROSC 30.1K
11
22
10
RVGDRV
97.6K
CVGDRV
10nF
RVDAC
3.5
VDAC
CVDAC
33nF
VGDRIVE
C135
1uF
Page 1 of 45
07/20/2005
1 page  
IR3084
PARAMETER
TEST CONDITION
VRRDY OUTPUT
Output Voltage
Leakage Current
I(VRRDY) = 4mA
V(VRRDY) = 5.5V
OSCILLATOR
Switching Frequency
Peak Voltage (4.8V typical,
measured as % of VBIAS)
Valley Voltage (0.9V typical,
measured as % of VBIAS)
DRIVER BIAS REGULATOR
REGSET Bias Current
1.5V ≤ V(REGSET) ≤ VCC – 1.5V
Input Offset Voltage
Short Circuit Current
Dropout Voltage
1.5V ≤ V(REGSET) ≤ VCC – 1.5V,
100µA ≤ I(REGDRV) ≤ 10mA
V(REGDRV) = 0V,
1.5V ≤ V(REGSET) ≤ VCC – 1.5V,
Note 1
I(REGDRV) = 10mA, Note 1
VCC UNDER−VOLTAGE LOCKOUT
Start Threshold
Stop Threshold
Hysteresis
Start – Stop
GENERAL
VCC Supply Current
VOSNS− Current
−0.3V ≤ VOSNS− ≤ 0.3V,
All VID Codes
MIN TYP MAX UNIT
150 300 mV
0 10 µA
450 500 550 kHz
70 72 74 %
10 13 15 %
−112 −99 −85
µA
−12 0
12 mV
10 20 50 mA
0.4 0.87 1.33
V
9.3 9.9 10.3 V
8.5 9.1 9.5
V
575 800 1000 mV
9
−1.45
14
−1.3
18
−0.75
mA
mA
Note 1: Guaranteed by design but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors
IR3084
+
"FAST"
VDAC
-
+
-
ISOURCE
ISINK
VDAC
BUFFER
AMP
200 OHM
EAOUT
ERROR
AMP
FB
VSETPT
OCSET
VDAC
IOFFSET IROSC
IROSC IOCSET
RVDAC
CURRENT
SOURCE
GENERATOR
ROSC
BUFFER
AMP
CVDAC
ROSC
+
1.2V
-
VOSNS-
ROSC
Page 5 of 45
Figure 1 – System Set Point Test Circuit
200 OHM
SYSTEM
SET POINT
VOLTAGE
07/20/2005
5 Page 
IR3084
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side
sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they
suffer from peak−to−average errors. These errors will show in many ways but one example is the effect of
frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10%
larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense
amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all
additional sources of peak−to−average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 6. Its gain
decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (−1470 ppm/ºC). This
reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the
Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature
compensation of the load line is required.
The current sense amplifier can accept positive differential input up to 100mV and negative up to −20mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC
and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the
phases are tied together and the voltage on the share bus represents the average inductor current through all the
inductors and is used by the Control IC for voltage positioning and current limit protection.
vL
iL L
RL
Vo
Rs
CSA
CO
Cs
vc
Co
Figure 6 – Inductor Current Sensing and Current Sense Amplifier
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each Phase
IC. The output of the current sense amplifier is compared with the share bus less a nominal 20mV offset. If
current in a phase is smaller than the average current, the share adjust amplifier of the phase will activate a
current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The
crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the
share loop does not interact with the output voltage loop.
Page 11 of 45
07/20/2005
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IR3084.PDF ] | |
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