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PDF XCR3032 Data sheet ( Hoja de datos )
| Número de pieza | XCR3032 | |
| Descripción | 32 Macrocell CPLD | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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APPLICATION NOTEwww.DataSheet4UTh.cisomproduct has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.
0
R XCR3032: 32 Macrocell CPLD
DS038 (v1.3) October 9, 2000
0 14* Product Specification
Features
• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• High speed pin-to-pin delays of 8ns
• Ultra-low static power of less than 35 µA
• 100% routable with 100% utilization while all pins and
all macrocells are fixed
• Deterministic timing model that is extremely simple to
use
• Two clocks available
• Programmable clock polarity at every macrocell
• Support for asynchronous clocking
• Innovative XPLA™ architecture combines high speed
with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard
and Xilinx CAE tools
• Reprogrammable using industry standard device
programmers
• Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
• Programmable global 3-state pin facilitates ‘bed of nails'
testing without using logic resources
• Available in both PLCC and VQFP packages
Description
The XCR3032 CPLD (Complex Programmable Logic
Device) is the first in a family of CoolRunner® CPLDs from
Xilinx. These devices combine high speed and zero power
in a 32 macrocell CPLD. With the FZP design technique,
the XCR3032 offers true pin-to-pin speeds of 8 ns, while
simultaneously delivering power that is less than 35 µA at
standby without the need for “turbo bits” or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cas-
caded chain of pure CMOS gates, the dynamic power is
also substantially lower than any competing CPLD. These
devices are the first TotalCMOS PLDs, as they use both a
CMOS process technology and the patented full CMOS
FZP design technique. For 5V applications, Xilinx also
offers the high speed XCR5032 CPLD that offers pin-to-pin
speeds of 6 ns.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 8 ns PAL path with five ded-
icated product terms per output. This PAL path is joined by
an additional PLA structure that deploys a pool of 32 prod-
uct terms to a fully programmable OR array that can allo-
cate the PLA product terms to any output in the logic block.
This combination allows logic to be allocated efficiently
throughout the logic block and supports as many as 37
product terms on an output. The speed with which logic is
allocated from the PLA array to an output is only 2.5 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 10.5 ns from any pin to
any other pin. In addition, logic that is common to multiple
outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR3032 CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
The XCR3032 CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BP Microsystems, SMS, and others.
DS038 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
1
1 page  
This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.
XCR3032: 32 Macrocell CPLD
R
Simple Timing Model
Figure 5 shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other architectures, the user
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR3032 device, the user knows up front that if a given
output uses five product terms or less, the tPD = 8 ns, the
tSU = 6.5 ns, and the tCO = 7.5 ns. If an output is using six to
37 product terms, an additional 2.5 ns must be added to the
tPD and tSU timing parameters to account for the time to
propagate through the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to Figure 6 and Table 1 showing the ICC vs.
Frequency of our XCR3032 TotalCMOS CPLD.
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
D
REGISTERED
Q tCO
OUTPUT PIN
GLOBAL CLOCK PIN
Figure 4: CoolRunner Timing Model
SP00441
5
www.xilinx.com
DS038 (v1.3) October 9, 2000
1-800-255-7778
5 Page 
This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.
XCR3032: 32 Macrocell CPLD
R
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
Parameter
10 12
tPD_PAL
tPD_PLA
Propagation delay time, input (or feedback node) to output through PAL
Propagation delay time, input (or feedback node) to output through
PAL + PLA
Min. Max. Min. Max.
2 10 2 12
3 12.5 3 15
tCO
tSU_PAL
tSU_PLA
tH
tCH
tCL
tR
tF
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
tPDF_PLA
Clock to out (global synchronous clock from pin)
2
Setup time (from input or feedback node) through PAL
8
Setup time (from input or feedback node) through PAL + PLA
10.5
Hold time
Clock High time
4
Clock Low time
4
Input rise time
Input fall time
Maximum FF toggle rate2 (1/tCH + tCL)
Maximum internal frequency2 (1/tSUPAL + tCF)
Maximum external frequency2 (1/tSUPAL + tCO)
Output buffer delay time
125
64.5
58.8
Input (or feedback node) to internal feedback node delay time through PAL
Input (or feedback node) to internal feedback node delay time through PAL
+ PLA
9
0
20
20
1.5
8
10.5
2
10.5
13.5
5
5
100
50
47
11
0
20
20
1.5
10.5
13.5
tCF Clock to internal feedback delay time
tINIT Delay from valid VCC to valid reset
tER Input to output disable3
tEA Input to output valid
tRP Input to register preset
tRR Input to register reset
7.5 9.5
50 50
16 19
16 19
17 20
20 23
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 2 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
11
www.xilinx.com
DS038 (v1.3) October 9, 2000
1-800-255-7778
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet XCR3032.PDF ] | |
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