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PDF L6563A Data sheet ( Hoja de datos )

Número de pieza L6563A
Descripción ADVANCED TRANSITION-MODE PFC CONTROLLER
Fabricantes ST Microelectronics 
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L6563
L6563A
Advanced transition-mode PFC controller
General features
Transition-mode control of PFC pre-regulators
Very precise adjustable output overvoltage
protection
Tracking boost function
Protection against feedback loop failure
(Latched shutdown)
Interface for cascaded converter's PWM
controller
Input voltage feedforward (1/V2)
Remote ON/OFF control
Low (90µA) start-up current
5mA max. quiescent current
1.5% (@ TJ = 25°C) internal reference voltage
-600/+800 mA totem pole gate driver with
active pull-down during UVLO
SO14 package
Block diagram
SO-14
Applications
PFC pre-regulators for:
HI-END AC-DC adapter/charger
Desktop PC, server, WEB server
IEC61000-3-2 OR JEIDA-MITI compliant
SMPS, in excess of 250W
Order code
Part number
L6563
L6563TR
L6563A
L6563ATR
Package
SO-14
SO-14
SO-14
SO-14
Packaging
Tube
Tape & Reel
Tube
Tape & Reel
TBO
V CC
GND
ZCD
INV
COMP
MULT
VFF
TRACKING
BOOST
6 1:1
CURRENT
MIRROR
1:1
BUFFER
3V
14
1
23
5
from
VFF
1 / V2
Ideal diode
2.5V
-
+
VOLTAGE
REGULATOR
MULTIPLIER
V o lta g e
r e fe r e n c e s
-+
LINE VOLTAGE
FEEDFORWARD
1.7V
-+
LEADING-EDGE
BLANKING
4
V b ia s
(INTERNAL SUPPLY BUS)
INDUCTOR
SATURATION
DETECTION
( not in L6563A )
SAT
Q
V CC
12
11
1.4V
0.7V
UVLO
R1 COMPARATOR
RQ
S
15 V
+
R2
-
VREF2
ZERO CURRENT
DETECTOR
UVLO
D riv e r
Starter
OFF
STARTER
13
0.2V
0.3V
CS
GD
RUN
10
-
0.52V
0.62V
ON/OFF CONTROL
(BROWNOUT DETECTION)
D IS A B L E
9
PWM_STOP
LATCH
SAT
Vbias FEEDBACK
F A IL U R E
8 DETECTION
PWM_LATCH
PFC_OK
7
2.5V
November 2006
Rev 3
1/37
www.st.com
37

1 page




L6563A pdf
L6563 - L6563A
Description
Table 1. Pin description (continued)
Pin N° Name
Description
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
1 INV The pin normally features high impedance but, if the tracking boost function is used, an
internal current generator programmed by TBO (pin 6) is activated. It sinks current from the
pin to change the output voltage so that it tracks the mains voltage.
Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected
6
TBO
between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way,
the output voltage is changed proportionally to the mains voltage (tracking boost). If this
function is not used leave this pin open.
PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
voltage of the PFC pre-regulator through a resistor divider and is used for protection
purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes
almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high.
7 PFC_OK Normal operation can be resumed only by cycling the Vcc. This function is used for
protection in case the feedback loop fails.
If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is
considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these
functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V.
Output pin for fault signaling. During normal operation this pin features high impedance. If
either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of
8 PWM_LATCH L6563A is detected the pin is asserted high. Normally, this pin is used to stop the operation
of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of
its PWM controller. If not used, the pin will be left floating.
Output pin for fault signaling. During normal operation this pin features high impedance. If
the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled
9 PWM_STOP to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC
converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used,
the pin will be left floating.
Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and
brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC
10
RUN
restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either
directly or through a resistor divider to use this function as brownout (AC mains
undervoltage) protection, tie to INV (pin 1) if the function is not used.
11
ZCD
Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-
going edge triggers MOSFET’s turn-on.
12
GND
Ground. Current return for both the signal part of the IC and the gate driver.
Gate driver output. The totem pole output stage is able to drive power MOSFET’s and
13 GD IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of
this pin is clamped at about 12V to avoid excessive gate voltages.
14
VCC
Supply Voltage of both the signal part of the IC and the gate driver.
5/37

5 Page





L6563A arduino
L6563 - L6563A
5 Typical electrical performance
Typical electrical performance
Figure 3. Supply current vs supply voltage
Icc
(m A)
10
5
1
0.5
0.1
0.05
0.01
0.005
Co = 1nF
f = 70 kHz
Tj = 25°C
0
0
5 10 15 20 25
Vcc(V)
Figure 5. IC consumption vs TJ
Icc 10
(m A)
5
2
O perating
Q uiescent
1
Vcc = 12 V
0.5 C o = 1 nF
f = 70 kHz
0 .2
D isabled or
during O V P
Latched off
0 .1
0.05 B efore start-up
0 .0 2
-50
0
50 100 150
Tj (°C)
Figure 7. Start-up & UVLO vs TJ
12.5
VCC-ON
(V) 12
11.5
11
10.5
10
VCC-OFF 9.5
(V)
9
-50
0 50
Tj (°C)
100
150
Figure 4. VCC Zener voltage vs TJ
V c cz (pin 14 )
(V) 28
27
26
25
24
23
22
-50
0 50 100 150
Tj (°C)
Figure 6. Feedback reference vs TJ
VREF (pin 1)
(V) 2.6
2.55
Vcc = 12 V
2.5
2.45
2.4
-50
0 50 100 150
Tj (°C)
Figure 8. E/A output clamp levels vs TJ
VCOMP (pin 2)
7
(V)
6 Upper clam p
5
Vcc = 12 V
4
3
2 Lower clam p
1
-50 0
50
Tj (°C)
100
150
11/37

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