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PDF IDT74ALVCH374 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVCH374 | |
| Descripción | 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS OCTAL POSITIVE
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
IDT74ALVCH374
ADVANCE
INFORMATION
FEATURES:
– 0.5 MICRON CMOS Technology
– Typical tSK(o) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm TSSOP packages
– Extended commercial range of -40°C to +85°C
– VCC = 3.3V ±0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– VCC = 2.5V ±0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH374:
– High Output Drivers: ±24mA
– Suitable for heavy loads
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
Functional Block Diagram
DESCRIPTION:
This octal postive edge-triggered D-type flip-flop is built using advanced
dual metal CMOS technology. The ALVCH374 device is particularly
suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. On the positive transition of the clock (CLK)
input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup
components. OE does not affect internal operations of the latch. Old data
can be retained or new data can be entered while the outputs are in the
high-impedance state.
The ALVCH374 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH374 has a “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
1
OE
11
CLK
3
1D
C1
1D
2 1Q
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
MARCH 1999
DSC-4473/-
1 page  
IDT74ALVCH374
3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
VLOAD
VIH
VT
VLZ
VHZ
CL
VCC(1)= 3.3V ±0.3V
6
2.7
1.5
300
300
50
VCC(1) = 2.7V
6
2.7
1.5
300
300
50
VCC(2)= 2.5V ±0.2V Unit
2 x Vcc
V
Vcc V
VCC / 2
V
150 mV
150 mV
30 pF
ALVC Link
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC
VLOAD
Open
Pulse(1, 2)
Generator
VIN
VOUT
D .U .T .
500Ω
GND
RT
500Ω
CL
DEFINITIONS:
ALVC Link
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
ENABLE AND DISABLE TIMES
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
VIH
VT
0V
OUTPUT SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
V L O A D /2
VT
tPHZ
VT
0V
V L O A D /2
VLZ
VOL
VOH
VHZ
0V
NOTE:
ALVC Link
1. Diagram shown for input Control Enable-LOW and input Control
SEDiTsab-lUe-HPIG,HH. OLD, AND RELEASE TIMES
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
VLOAD
GND
Open
OUTPUT SKEW - TSK (x)
INPUT
tPLH1
tPHL1
OUTPUT 1
tSK (x)
tSK (x)
OUTPUT 2
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
ALVC Link
DATA
INPUT
T IM IN G
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
PULSE WIDTH
L O W -H IG H -LO W
PULSE
H IG H -L O W -H IG H
PULSE
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
NOTES:
ALVC Link
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
tSU tH
tREM
tSU tH
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
ALVC Link
VT
tW
VT
ALVC Link
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVCH374.PDF ] | |
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