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PDF TDA8742H Data sheet ( Hoja de datos )

Número de pieza TDA8742H
Descripción Satellite sound circuit
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
TDA8742; TDA8742H
Satellite sound circuit with noise
reduction
Product specification
Supersedes data of November 1992
File under Integrated Circuits, IC02
October 1994
Philips Semiconductors

1 page




TDA8742H pdf
Philips Semiconductors
Satellite sound circuit with noise reduction
Product specification
TDA8742; TDA8742H
SYMBOL
CDC L
CDC M
CDC R
n.c.
n.c.
PIN
SDIP42
40
41
42
PIN
QFP44
36
37
38
12
44
DESCRIPTION
DC decoupling capacitor (left)
DC decoupling capacitor (main)
DC decoupling capacitor (right)
not connected
not connected
October 1994
Fig.2 Pin configuration (SDIP42).
5

5 Page





TDA8742H arduino
Philips Semiconductors
Satellite sound circuit with noise reduction
Product specification
TDA8742; TDA8742H
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Secondary channels 1 and 2 - HF inputs pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) and
limiters
VIN1,IN2(rms)
Vi(rms)
Ri
input sensitivity (RMS value)
input signal level (RMS value)
input resistance
S/N(A) = 40 dB
0.8 1.5 mV
− − 200 mV
260 330 380
Secondary channels 1 and 2 - PLL FM demodulators (input selector in position 1)
fCCO1
fCCO2
fOS1/2
RS1, S2
free running frequency PLL1
free running frequency PLL2
lock range of PLLs
series resistance for optimum
frequency response
adjustment
note 3
10.7 MHz
10.52 MHz
10
11.5 MHz
0 0.68 2.2 k
VCDCL,CDCR(rms)
PLL output voltage pins 40 and pins to be left open-circuit 9 mV
42 (36 and 38) (RMS value)
VCDCL,CDCR
spread of PLL output voltage
over lock range
− − ±1 dB
Secondary channels - overall performance of LPF and NR (output selectors in position 1)
Ro output resistance for 75 µs
de-emphasis pins 36 and 32
(32 and 28)
1.9 2.3 2.6 k
Ri input resistance of output
amplifiers pins 35 and 33
(31 and 29)
95 150 200 k
VOL,OR
output voltage level pins 25
and 24 (21 and 20)
note 4
8 6 4 dBV
UBS
unbalance voltage outputs
pins 25 and 24 (21 and 20)
note 4
1
+1 dB
THD
total harmonic distortion
note 4
0.1 0.5 %
S/N(A)
signal-to-noise ratio
A-weighted; note 4
72 80
dB
Ro
output resistance pins 25 and note 4
92 125 150
24 (21 and 20)
MUTEatt
mute attenuation
output selector in
position 6; note 4
74 − − dB
αS/S crosstalk attenuation between note 5 74 dB
secondary channels
αM/S
crosstalk attenuation from main note 6
channel to secondary
74 dB
Voffset(DC)
DC offset voltage on
attack/recovery capacitors
pins 29, 39 (25, 35)
all PLLs locked; f = 0 14 16 20 mV
SVRR
supply voltage ripple rejection VRR = 100 mV; fi = 70 Hz
25
dB
October 1994
11

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