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PDF ISL12029 Data sheet ( Hoja de datos )

Número de pieza ISL12029
Descripción Real Time Clock/Calendar
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL12029 Hoja de datos, Descripción, Manual

ISL12029, ISL12029ANOc1NTo-8nOR8taE8RcD-CEItNaOCotTMOauErMMSRTMhESeeNIcELehDNtonEDriDcEwaDFlwOSRwRuE.ipPnNpLtEeoArWrsCt iCElD.ceMEonSEmtIeNDG/rTetNsaccStember 16, 2010
FN6206.10
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12029 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (open drain
output), intelligent battery backup switching, CPU
Supervisor, integrated 512x8-bit EEPROM configured in 16
bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12029 and ISL12029A Power Control Settings are
different. The ISL12029 uses the Legacy Mode Setting, and
the ISL12029A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12029A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I2C
Communications During Battery Backup” on page 24 for
important details.
Pinout
ISL12029, ISL12029A
(14 LD TSSOP, SOIC)
TOP VIEW
X1
X2
NC
NC
NC
RESET
GND
1
2
3
4
5
6
7
14 VDD
13 VBAT
12 IRQ/FOUT
11 NC
10 NC
9 SCL
8 SDA
NC = No internal connection
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation:
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• CPU Supervisor Functions
- Power-On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s, 1.5s)
• I2C Interface
- 400kHz Data Transfer Rate
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/AutomotivePAR
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2005, 2006, 2008, 2010.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

1 page




ISL12029 pdf
ISL12029, ISL12029A
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
PARAMETER
CONDITIONS
tRPD
tPURST
VRVALID
VDD Detect to RESET LOW
Power-Up Reset Time-Out Delay
Minimum VDD for Valid RESET
Output
VRESET
ISL12029-4.5A Reset Voltage Level
ISL12029 Reset Voltage Level
ISL12029-3 Reset Voltage Level
ISL12029-2.7A Reset Voltage Level
ISL12029-2.7 Reset Voltage Level
tWDO Watchdog Timer Period
32.768kHz crystal between X1
and X2
tRST
Watchdog Timer Reset Time-Out
Delay
32.768kHz crystal between X1
and X2
tRSP I2C Interface Minimum Restart Time
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature 75°C
MIN TYP
(Note 16) (Note 11)
500
100 250
1.0
MAX
(Note 16)
400
4.59 4.64
4.69
4.33 4.38
4.43
3.04 3.09
3.14
2.87 2.92
2.97
2.58 2.63
2.68
1.70 1.75 1.801
725 750
775
225 250
275
225 250
275
1.2
>2,000,000
50
UNITS
ns
ms
V
V
V
V
V
V
s
ms
ms
ms
µs
Cycles
Years
NOTES
13
Serial Interface (I2C) Specifications - DC/AC Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
VIL SDA, and SCL Input Buffer LOW
Voltage
VIH SDA, and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer
Hysteresis
SBIB = 1 (Under VDD mode)
SBIB = 1 (Under VDD mode)
SBIB = 1 (Under VDD mode)
-0.3
0.7 x VDD
0.05 x VDD
VOL SDA Output Buffer LOW Voltage
ILI Input Leakage Current on SCL
ILO I/O Leakage Current on SDA
TIMING CHARACTERISTICS
fSCL
SCL Frequency
tIN Pulse Width Suppression Time at
SDA and SCL Inputs
IOL = 4mA
VIN = 5.5V
VIN = 5.5V
Any pulse narrower than the max
spec is suppressed.
0
tAA
tBUF
tLOW
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
1300
TYP
0.1
0.1
MAX
(Note 16)
0.3 x VDD
UNITS
V
NOTES
VDD + 0.3
V
V
0.4 V
10 µA
10 µA
400 kHz
50 ns
900 ns
ns
ns
5 FN6206.10
December 16, 2010

5 Page





ISL12029 arduino
ISL12029, ISL12029A
requires a new operation. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 (status register) supports a single
byte read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are
read by performing a sequential read. The read instruction
latches all Clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential
read of the CCR will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read of the CCR, the address remains at the previous
address +1 so the user can execute a current address read
of the CCR and continue reading the next Register.
Real Time Clock Registers (Volatile)
SC, MN, HR, DT, MO, YR: Clock/Calendar Registers
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 00 to 59,
HR (Hour) is 1 to 12 with an AM or PM indicator (H21-bit) or
0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is
1 to 12, YR (Year) is 0 to 99.
DW: Day of the Week Register
This register provides a Day of the Week status and uses
three bits DY2 to DY0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as ‘0’.
Y2K: Year 2000 Register
Can have value 19 or 20. As of the date of the introduction of
this device, there would be no real use for the value 19 in a
true real time clock, however.
24-Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and
H21-bit functions as an AM/PM indicator with a ‘1’,
representing PM. The clock defaults to standard time with
H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4.
Status Register (SR) (Volatile)
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
ADDR 7 6 5 4 3 2 1 0
003Fh BAT AL1 AL0 OSCF 0 RWEL WEL RTCF
Default 0 0 0 0 0 0 0 1
BAT: Battery Supply
This bit set to “1” indicates that the device is operating from
VBAT, not VDD. It is a read-only bit and is set/reset by
hardware (ISL12029 internally). Once the device begins
operating from VDD, the device sets this bit to “0”.
AL1, AL0: Alarm Bits
These bits announce if either alarm 0 or alarm 1 match the
real time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read
operation resets the flags. Note: Only the AL bits that are set
when an SR read starts will be reset. An alarm bit that is set
by an alarm occurring during an SR read operation will
remain set after the read operation is complete.
OSCF: Oscillator Fail Indicator
This bit is set to "1" if the oscillator is not operating or is
operating but has clock jitter, which does not affect the
accuracy of RTC counting. The bit is set to "0" if the oscillator
is functioning and does not have clock jitter. This bit is read
only, and is set/reset by hardware.
RWEL: Register Write Enable Latch
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit do
not cause a non-volatile write cycle, so the device is ready
for the next operation immediately after the stop condition. A
write to the CCR requires both the RWEL and WEL bits to be
set in a specific sequence.
WEL: Write Enable Latch
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the
LOW (disabled) state. While the WEL bit is LOW, writes to
the CCR address will be ignored, although acknowledgment
is still issued. The WEL bit is set by writing a “1” to the WEL
bit and zeroes to the other bits of the Status Register. Once
set, WEL remains set until either reset to 0 (by writing a “0”
to the WEL bit and zeroes to the other bits of the Status
Register) or until the part powers up again. Writes to WEL bit
do not cause a non-volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit
This bit is set to a “1” after a total power failure. This is a
read only bit that is set by hardware (ISL12029 internally)
when the device powers up after having lost all power to
11 FN6206.10
December 16, 2010

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