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PDF PE9701 Data sheet ( Hoja de datos )
| Número de pieza | PE9701 | |
| Descripción | Integer-N PLL Rad Hard | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
Peregrine’s PE9701 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE9701 features a 10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE9701 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Figure 1. Block Diagram
Product Specification
PE9701
3000 MHz UltraCMOS™ Integer-N PLL
Rad Hard for Space Applications
Features
• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector with charge
pump
• Serial, parallel or hardwired
programmable
• Ultra-low phase noise
• SEU < 10-9 errors / bit-day
• 100 Krad (Si) total dose
• 44-lead CQFJ
Fin Prescaler
Fin 10/11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
PD_U
Phase
Detector
PD_D
Charge
Pump
CP
fc
Document No. 70-0035-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
1 page  
PE9701
Product Specification
Table 2. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD Supply voltage
VI Voltage on any input
II DC into any input
-0.3 4.0
-0.3
VDD
+ 0.3
-10 +10
V
V
mA
IO DC into any output
Tstg
Storage temperature
range
-10 +10
-65 150
mA
°C
Table 3. Operating Ratings
Symbol Parameter/Conditions Min Max Units
VDD Supply voltage
TA
Operating ambient
temperature range
2.85 3.15
-40 85
V
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level Units
VESD
ESD voltage (Human Body
Model) – Note 1
1000
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ
IDD Operational supply current;
Prescaler disabled
Prescaler enabled
Digital Inputs: All except fr, Fin, Fin
VIH High level input voltage
VIL Low level input voltage
IIH High level input current
IIL Low level input current
Reference Divider input: fr
IIHR High level input current
IILR Low level input current
R0 Input: R0
IIHRO High level input current
IILRO Low level input current
Counter and phase detector outputs: fc, fp.
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Lock detect outputs: Cext, LD
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
Iout = 6 mA
Iout = -3 mA
0.7 x VDD
10
24
-1
-100
-5
VDD - 0.4
VOLC
Output voltage LOW, Cext
VOHC
Output voltage HIGH, Cext
VOLLD
Output voltage LOW, LD
Charge Pump output: CP
Iout = 100 µA
Iout = -100 µA
Iout = 6 mA
VDD - 0.4
ICP - Source
ICP – Sink
ICPL
ICP – Source
vs. ICP Sink
Drive current
Drive current
Leakage current
Sink vs. source mismatch
VCP = VDD / 2
VCP = VDD / 2
1.0 V < VCP < VDD – 1.0 V
VCP = VDD / 2,
TA = 25° C
-2.6 -2
1.4 2
-1
ICP vs. VCP
Output current magnitude variation vs. voltage
V < VCP < VDD – 1.0 V
TA = 25° C
Max
31
Units
mA
mA
0.3 x VDD
+70
V
V
µA
µA
+100
µA
µA
+70 µA
µA
0.4 V
V
0.4 V
V
0.4 V
-1.4 mA
2.6 mA
1 µA
25 %
25 %
Document No. 70-0035-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
5 Page 
PE9701
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
Reserved**
Reserved**
Power down
Counter load
MSEL output
Prescaler output
fp, fc OE
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Smode inputs.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output (fmain) onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “high”. If the divided reference leads
the divided VCO in phase or frequency (fr leads
fp), PD_U pulses “high”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
The signals from the phase detector couple
directly to a charge pump. PD_U controls a
current source at pin CP with constant amplitude
and pulse duration approximately the same as
PD_U. PD_D similarly drives a current sink at
pin CP. The current pulses from pin CP are low
pass filtered externally and then connected to the
VCO tune voltage. PD_U pulses result in a
current source, which increases the VCO
frequency; PD_D pulses result in a current sink,
which decreases VCO frequency.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2k Ω resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D. See Figure 4 for a
schematic of this circuit.
Document No. 70-0035-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PE9701.PDF ] | |
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