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PDF DS2168 Data sheet ( Hoja de datos )

Número de pieza DS2168
Descripción (DS2167 / DS2168) ADPCM Processor
Fabricantes Dallas Semiconducotr 
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DS2167/DS2168
DS2167/DS2168
ADPCM Processor
FEATURES
Speech compression chip compatible with standard
ADPCM algorithms:
– DS2167 supports “new” T1Y1 recommenda-
tions (July 1986) and “new” CCITT G.721 rec-
ommendations
– DS2168 supports “old” CCITT G.721 recom-
mendations
Dual independent channel architecture – device may
be programmed to perform full duplex, 2-channel ex-
pansions, or 2-channel compressions
Interconnects directly with µ-law or A-law codec/filter
devices
Serial PCM and control port interfaces minimize “glue
logic” in multiple channel applications
– On-chip channel counters identify input and out-
put timeslots in TDM-based systems
– Unique addressing scheme simplifies device
control; 3-wire port shared among 64 devices
– Bypass and idle features allow dynamic alloca-
tion of channel bandwidth, minimize system
power requirements
Hardware mode intended for stand-alone use
– No host processor required
– Ideal for voice mail applications
28-pin surface-mount package available, designated
DS2167Q/DS2168Q
PIN ASSIGNMENT
RST
TM0
TM1
A0
A1
A2
A3
A4
A5
SPS
MCLK
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24 VDD
23 YIN
22 CLKY
21 FSY
20 YOUT
19 CS
18 SDI
17 SCLK
16 XOUT
15 FSX
14 CLKX
13 XIN
24-Pin DIP (600 MIL)
NC 5 4 3 2 1 28 27 2625 FSY
A0 6
24 YOUT
A1 7
23 CS
A2 8
22 SDI
A3 9
21 SCLK
A4 10
20 XOUT
A5
11
12 13 14 15
16 17 1819
NC
28-Pin PLCC
DESCRIPTION
The DS2167 and DS2168 are dedicated digital signal
processor (DSP) CMOS chips optimized for Adaptive
Differential Pulse Code Modulation (ADPCM) based
compression algorithms. The devices halve the trans-
mission bandwidth of “toll quality” voice from 64K to 32K
bits/second and are utilized in PCM-based telephony
networks.
022698 1/15

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DS2168 pdf
DS2167/DS2168
CODEC/FILTER HARDWARE MODE INTERCONNECT Figure 2
TRANSMIT FRAME SYNC
TRANSMIT DATA CLOCK
-5.0 V
TRANSMIT
ANALOG
INTERFACE
RECEIVE
ANALOG
INTERFACE
VCC
MCLKX
VBB
DX
GNDA
FSX
TSX
VFXI+
VFSI-
GSX
BCLKX
DR
FSR
BCLK/
CLKSEL
MCLK/PDN
VFRO
RECEIVE DATA CLOCK
RECEIVE FRAME SYNC
POWER ON RESET
(DS1231)
RST
SCLK
XIN
FSX
CLKX
YOUT
FSY
CLKY
SPS
TM0
TM1
VSS
VDD
A0
A5
A2
XOUT
YIN
A3
A4
A1
SDI
CS
MCLK
TP3054 (µ-LAW)
TP3057 (µ-LAW)
TRANSMIT DATA
RECEIVE DATA
POWER DOWN
ACTIVE
10 MHz CLOCK
NOTE:
Suggested Codec/Filters
TP305X
National Semiconductor
ETC505X SGS–Thomson Microelectronics
MC1455XX Motorola
TCM29CXX Texas Instruments
HD44238C Hitachi
*other generic Codec/Filter devices can be substituted.
SOFTWARE MODE
Tying SPS high enabled the software mode. In this
mode, a host microcontroller writes configuration data
to the DS2167/DS2168 serial port via inputs SCLK, SDI,
and CS. Independent control and timeslot registers es-
tablish operating characteristics for the X-side and Y-
side PCM interfaces.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the
first byte written to the serial port; it identifies which of 64
possible ADPCM processors sharing the port wiring is
to be updated. Address data must match that at inputs
A0–A5. If no match occurs, the device ignores the fol-
lowing configuration data. If an address match occurs,
the next three bytes written are accepted as control, in-
put and output timeslot data. Bit ACB.6 determines
which side (X or Y) of the device is to be updated.
CONTROL REGISTER
The control register establishes idle, algorithm reset,
bypass, data format and channel coding for the selected
PCM interface.
The X and Y side PCM interfaces may be independently
disabled (output tri-stated) via IPD; when IPD is set for
022698 5/15

5 Page





DS2168 arduino
DS2167/DS2168
PCM INTERFACE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MCLK Period
MCLK Pulse Width
MCLK Rise and Fall Times
CLKX, CLKY Period
CLKX, CLKY Pulse Width
CLKX, CLKY Rise and Fall Times
Hold Time from CLKX, CLKY to
FSX, FSY
tPM
tWMH,
tWML
tRM, tFM
tPXY
tWXYH,
tWXYL
tRXY, tFXY
tHOLD
Setup Time from FSX, FSY to
CLKX, CLKY low
tSF
Hold Time from CLKX, CLKY low
to FSX, FSY low
tHF
XIN, YIN Setup to CLKX, CLKY
low
tSD
XIN, YIN Hold to CLKX, CLKY
low
tHD
Delay Time from CLKX, CLKY to
Valid XOUT, YOUT
tDXYO
Delay Time from CLKX, CLKY to
XOUT, YOUT Tri-stated
tDXYZ
MIN
45
244
100
0
50
100
50
50
10
20
(0°C to 70°C, VDD = 5V + 10%)
TYP
MAX
UNITS NOTES
100 ns 5
50 55 ns
5 10 ns
488 5208 ns
244 ns
4
10 20 ns
ns 1
ns 1
ns 1
ns 1
ns 1
150 ns
2
150 ns 1,2,3
NOTES:
1. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times.
2. Load = 150 pF + 2 LSTTL loads.
3. For LSB of PCM byte or ADPCM nibble.
4. Maximum width of FSX, FSY is one CLKX, CLKY period.
5. MCLK = 10 MHz + 500 ppm.
022698 11/15

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