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PDF U63716 Data sheet ( Hoja de datos )
| Número de pieza | U63716 | |
| Descripción | CAPSTORE 2K X 8 NVSRAM | |
| Fabricantes | ZMD | |
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U63716
CapStore 2K x 8 nvSRAM
Features
Description
S CMOS non- volatile static RAM
2048 x 8 bits
S 70 ns Access Time
S 35 ns Output Enable Access Time
S ICC = 15 mA at 200 ns Cycle Time
S Unlimited Read and Write Cycles
to SRAM
S Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
S Software initiated STORE
S Automatic STORE Timing
S 106 STORE cycles to EEPROM
S 100 years data retention in
EEPROM
S Automatic RECALL on Power Up
S Software RECALL Initiation
S Unlimited RECALL cycles from
EEPROM
S Single 5 V ± 10 % Operation
S Operating temperature range:
0 to 70 °C
-40 to 85 °C
S QS 9000 Quality Standard
S ESD protection > 2000 V
(MIL STD 883C M3015.7)
S RoHS compliance and Pb- free
S Package: PDIP24 (600 mil)
The U63716 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In non-volatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U63716 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an integra-
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U63716 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63716 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 PDIP
7 24
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
April 7, 2005
1
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
Previous Data Valid
tv(A) (9)
tcR (1)
Address Valid
ta(A) (2)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU (10)
STANDBY
tdis(E) (5)
tPD (11)
tdis(G) (6)
Output Data Valid
U63716
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
tAVAV
tWLWH
tAVWL
tAVWH
tELWH
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tWLEH
tAVEL
tAVEH
tELEH
tDVEH
tEHDX
tEHAX
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
tsu(D)
th(D)
th(A)
tdis(W)
ten(W)
Min.
70
55
55
0
55
55
55
30
0
0
5
Max.
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 7, 2005
5
5 Page 
U63716
Device Operation
The U63716 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
SRAM READ
The U63716 performs a READ cycle whenever E and
G are LOW and W is HIGH. The address specified on
pins A0 - A10 determines which of the 2048 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of tcR. If the READ is initiated by E or G, the outputs will
be valid at ta(E) or at ta(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the tcR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
Automatic STORE
During normal operation, the U63716 will draw current
from VCC to charge up an integrated capacitor. This
stored charge will be used by the chip to perform a sin-
gle STORE operation. If the voltage on the VCC pin
drops below VSWITCH, the part will automatically discon-
nect the internal components from the external power
supply with a typical delay of 150 ns and initiate a
STORE operation with tPDSTORE max. 10 ms.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
SRAM READ and WRITE operations that are in pro-
gress after an automatic STORE cycle on power down
is requested are given time to complete before the
STORE operation is initiated.
During tDELAY multiple SRAM READ operations may
take place. If a WRITE is in progress it will be allowed a
time, tDELAY, to complete. Any SRAM WRITE cycles
requested after the VCC pin drops below VSWITCH will be
inhibited.
Automatic RECALL
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
VSWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the U63716 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U63716 software controlled STORE cycle is initia-
ted by executing sequential READ cycles from six spe-
cific address locations. By relying on READ cycles only,
the U63716 implements nonvolatile operation while
remaining compatible with standard 2K x 8 SRAMs.
During the STORE cycle, an erase of the previous non-
volatile data is performed first, followed by a parallel
programming of all the nonvolatile elements. Once a
STORE cycle is initiated, further inputs and outputs are
disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
1. Read addresses 000 (hex) Valid READ
2. Read addresses 555 (hex) Valid READ
3. Read addresses 2AA (hex) Valid READ
4. Read addresses 7FF (hex) Valid READ
5. Read addresses 0F0 (hex) Valid READ
6. Read addresses 70F (hex) Initiate STORE
Cycle
April 7, 2005
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet U63716.PDF ] | |
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