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PDF M1026 Data sheet ( Hoja de datos )

Número de pieza M1026
Descripción (M1025 / M1026) VCSO BASED CLOCK PLL
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Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M1025
32 M 1 0 2 6
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
FEATURES
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
19.44 or 38.88
77.76
155.52
622.08
PLL Ratio
(Pin Selectable)
(M1025) (M1026)
8 or 4
2
1
0.25
Output Clock
(MHz)
(Pin Selectable)
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
M1025/26
Loop Filter
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
MUX
0 R Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL
Phase
Detector
M/R Divider
LUT
M Divider
VCSO
P Divider
(1, 2, or TriState)
TriState
LOL
FOUT
nFOUT
2
P_SEL1:0
P Divider
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 1.0
Revised 28Jul2004
M1025/26 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

1 page




M1026 pdf
Integrated
Circuit
Systems, Inc.
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Implementation of single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50kto Vcc and 50kto ground. Figure 4 shows
the input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
LVCMOS/
LVTTL
DIF_REF0
nDIF_REF0
X
VCC
DIF_REF1 127
LVPECL
VCC
82
127
nDIF_REF1
82
REF_SEL
VCC
50k
50k
50k
VCC
50k
50k
50k
MUX
0
1
M1025/26
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127
and 82resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
PLL Operation
The M1025/26 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
Fvcso
=
Fin
×
M---
R
For the available M divider and R divider look-up table
combinations, Tables 3 and 4 on pg. 3 list the Total PLL
Ratio as well as Fin when using the M1025-11-155.5200 or
the M1026-11-155.5200. (“Ordering Information”, pg. 14.)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1025/26 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The P_SEL pin selects the value for the P divider: logic 1
sets P to 2, logic 0 sets P to 1. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Fout = --F----v---c---s---o---- = Fin × ------M-----------
P R× P
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M1025/26 Datasheet Rev 1.0
5 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

5 Page





M1026 arduino
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 150-175MHz,
LVPECL outputs terminated with 50to VCC - 2V
Symbol Parameter
Min Typ Max Unit Conditions
Power Supply VCC Positive Supply Voltage
3.135 3.3 3.465 V
ICC Power Supply Current
175 225 mA
All
Differential
Inputs
VP-P
VCMR
CIN
Peak to Peak Input Voltage
Common Mode Input
Input Capacitance
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
0.15
0.5
V
Vcc - .85 V
4 pF
Differential
Inputs with
Pull-down
IIH Input High Current (Pull-down)
IIL Input Low Current (Pull-down) DIF_REF0, DIF_REF1
Rpulldown Internal Pull-down Resistance
150 µA
VCC = VIN =
-5 µA 3.456V
50 k
Differential
Inputs
Biased to
VCC/2
IIH
IIL
Rbias
Input High Current (Biased)
Input Low Current (Biased)
Biased to Vcc/2
nDIF_REF0, nDIF_REF1
-150
150
See Figure 4
µA
µA
VIN =
0 to 3.456V
All LVCMOS
/ LVTTL
Inputs
VIH
VIL
CIN
Input High Voltage
Input Low Voltage
Input Capacitance
AUTO, REF_SEL,
MR_SEL3, MR_SEL2,
MR_SEL1, MR_SEL0,
P_SEL1, P_SEL0, NBW
2
-0.3
Vcc + 0.3 V
0.8 V
4 pF
LVCMOS /
LVTTL
Inputs with
Pull-down
IIH Input High Current (Pull-down) AUTO, REF_SEL,
MR_SEL3, MR_SEL2,
IIL Input Low Current (Pull-down) MR_SEL1, MR_SEL0,
Rpulldown Internal Pull-down Resistance P_SEL1, P_SEL0
150 µA
VCC = VIN =
3.456V
-5 µA
50 k
LVCMOS /
LVTTL
Inputs with
Pull-UP
IIH
IIL
Rpullup
Input High Current (Pull-UP)
Input Low Current (Pull-UP)
Internal Pull-UP Resistance
NBW
-150
50
5 µA
µA
VCC = 3.456V
VIN = 0 V
k
Differential
Outputs
LVCMOS
Output
VOH
VOL
VP-P
VOH
VOL
Output High Voltage
Output Low Voltage
FOUT, nFOUT
Peak to Peak Output Voltage 1
Output High Voltage
Output Low Voltage
LOL, REF_ACK
Vcc - 1.4
Vcc - 2.0
0.4
2.4
GND
Vcc - 1.0 V
Vcc - 1.7 V
0.85 V
VCC V
0.4 V
IOH= 1mA
IOL= 1mA
Note 1: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 12.
Table 10: DC Characteristics
M1025/26 Datasheet Rev 1.0
11 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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