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PDF CDB61884 Data sheet ( Hoja de datos )

Número de pieza CDB61884
Descripción Octal T1/E1/J1 Line Interface Evaluation Board
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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CDB61884
Octal T1/E1/J1 Line Interface Evaluation Board
Features
Description
Socketed CS61884 Octal Line Interface
Unit
Binding post connectors for power and line
interface connections
Components supplied for all operational
modes E1 75 , E1 120 and T1/J1 100
Socketed termination circuitry for easy
testing
Connector for IEEE 1149.1 JTAG Boundary
Scan
LED Indicators for Loss of Signal (LOS) and
power
Supports Hardware, Serial, and Parallel
Host Modes
Easy-to-use evaluation software
On-board socketed reference clock
oscillator
The CS61884 evaluation board is used to demostrate
the functions of a CS61884 Octal Line Interface Unit in
either E1 75 , E1 120 , or T1/J1 100 applications.
The evaluation board can be operated in either Hard-
ware Mode or Host Mode. In Hardware Mode, switches
and bed stake headers are used to control the line con-
figuration and channel operations for all eight channels.
In Host Mode (Serial or Parallel), the evaluation soft-
ware, switches, and bed stake headers are used to
control the line configuration and operating mode set-
tings for each channel.
In both Hardware and Host modes, the board may be
configured for E1 75 , E1 120 Ω, or T1/J1 100 oper-
ating modes. In both modes binding post connectors
provide easy connections between the line interface
connections of the CS61884 and any E1/T1 analyzing
equipment, which may be used to evaluate the CS61884
device. Bed stake headers allow easy access to each
channel’s clock and data I/O digital interface.
Eight LED indictors display the Loss of Signal (LOS)
conditions for each channel during Hardware and Host
modes. An LED indictor is used on the Interrupt pin to
indicate a change of state.
ORDERING INFORMATION
CS61884-IQ -40° to 85° C
CDB61884
144-pin LQFP
Evaluation Board
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR ‘02
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CDB61884 pdf
CDB61884
2. BOARD COMPONENT DESCRIPTIONS
2.1 Power Connections
Power for the evaluation board is supplied by an
external +3.3 V DC power supply. A +5 V DC
power supply can also be connected to the on-board
control logic. The LED labeled “D3” will illumi-
nate when power is supplied to the on-board con-
trol logic.
– Connect the +3.3 VDC power supply to the +3V
binding post and the +5 VDC power supply to
the +5 V binding post if 5 Volt logic is required
– Jumper J13 shown in Figure 2 allows all the
external logic on the evaluation board to be
connected to either +3 V or +5 V binding post.
J13
3V
2.2 Master Clock Selection
In both hardware and host modes, the MCLK pin is
configured by placing a short block on one of the
positions of bed stake header J1. Figure 3 shows
the different positions of the J1 bed stake header.
MCLK
J1
Data Recovery Mode
MCLK
J1
On-board Oscillator
V LO G IC
5V
O n-board logic connected
to + 3 V b in d in g p o st
J13
3V
V LO G IC
5V
MCLK
MCLK
J1 J1
External Clock Source Receivers Powered Down
O n-board logic connected
to +5 V binding post
Figure 2. On-board Logic Power Selection
– To measure the current consumption of only
the CS61884 device, place a short block on
Jumper J13 to connect the Vlogic power
supplies to the +5 V binding post. This will
isolate the CS61884 device from all the on-
board logic, to allow the current measurement
to be made at the +3 V binding post.
Figure 3. Master Clock Selections
– A 2.048 MHz clock oscillator is provided on the
evaluation board for use as the on-board clock
source for all E1 modes.
– A 1.544 MHz clock oscillator is also provided
with the evaluation board for use as the on-
board clock source for the T1/J1 operation
modes.
– A BNC connector (labeled J16) provides the
connection for an external clock source.
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CDB61884 arduino
CDB61884
4.3.1 Clear All Button Description
The CLR All Button shown Figure 14 is used to set
all the bits in the corresponding register to 0s. This
button is placed to the left of each register that has
write access.
Figure 14. Clear All Button
Figure 16. Read All Button
4.4 Write Button Description
The Write button shown in Figure Figure 17 writes
the bits of the corresponding register. This button is
located to the right of every register that allows
write access.
4.3.2 Write All Button Description
The Write All button shown in Figure 15 writes
every bit of every register on the current register
screen. This button is located in the bottom right
corner of each register screen.
Figure 15. Write All Button
Figure 17. Write Button
4.5 Read Button Description
The Read button shown in Figure 18 reads the bits
of the corresponding register. This button is located
to the right of every register.
4.3.3 Read All Button Description
The Read All button shown in Figure 16 reads ev-
ery bit of every register on the current register
screen. This button is located in the bottom left cor-
ner of each register screen.
Figure 18. Read Button
4.6 Program Exit Function
To exit any of the register screens simple press the
X in the top right hand corner of each screen. This
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