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PDF CDB61581 Data sheet ( Hoja de datos )
| Número de pieza | CDB61581 | |
| Descripción | Universal Line Interface Unit | |
| Fabricantes | Cirrus Logic | |
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CDB61581
Universal Line Interface Unit
Features
s Socketed CS61581 Universal Line Interface
s All Required Components for CS61581 Evaluation
s LED Status Indications for Alarm Conditions and
Operating Status
s Support for Hardware and Host Modes
Description
The evaluation board includes a socketed CS61581 line
interface device and all support components necessary
for evaluation. The board is powered by an external
+5 Volt supply.
The board may be configured for 100 Ω twisted-pair T1,
75 Ω coax E1, or 120 Ω twisted-pair E1 short and long
haul operations. Binding posts and bantam jacks are
provided for the line interface connections. Several
BNC connectors provide clock and data I/O at the sys-
tem interface. Reference timing may be derived from a
quartz crystal or an external reference clock. Four LED
indicators monitor device alarm conditions and operat-
ing status.
ORDERING INFO:
CDB61581
5V+ 0V
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
Hardware Control
and Mode Circuit
LED Status
Indicators
Serial Interface
Control Circuit
TTIP
TRING
RTIP
CS61581
XTALIN
RRING
MCLK
+5V
4.7 kΩ
XTL (optional)
XTALOUT
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
OCT ‘99
DS211DB2
1
1 page  
CDB61581
6. LED INDICATORS
The four-LED pack D1 indicates signal states on
LATN1, LATN2, LOS and NLOOP. The LOS
LED indicator illuminates when the line interface
receiver has detected a loss of signal. The NLOOP
LED indicates if Network Loopback is in opera-
tion. The LATN1/LATN2 LED’s indicate the at-
tenuation level of the received signal; reading how
much the incoming signal is below the nominal ex-
pected signal level. See Table 1 for details.
7. BUFFERING
Buffer U2 provides additional drive capability for
the SW1 and Host mode connections. The buffer
outputs are filtered with an (optional) RC network
(not initially populated) to reduce the transients
caused by buffer switching.
8. TRANSFORMER SELECTION
The evaluation board is supplied from the factory
with PE-64936 (1:1), PE-65351 (1:2) and T-1054
(1:1.5) transformers by Pulse Engineering. The
socket T1 on the board is for receive side trans-
former and T2 is for the transmit side. In the
matched impedance mode HDR1-HDR2 should be
placed in the MATZ positions, and in the low im-
pedance mode in the LOWZ positions. Please see
Table 2 for details on transformers selection.
9. PROTOTYPING AREA
An ample prototyping area with power supply and
ground connections is provided on the evaluation
board. This area can be used to develop and test a
variety of additional circuits such as framer devic-
es, system synchronizer PLLs, or specialized inter-
face logic.
LATN1
ON
OFF
ON
OFF
LATN2
ON
OFF
OFF
ON
Attenuation Level (dB)
0
7.5
15
22.5
Table 1. LATN Settings
Mode
T1 (100 Ω)/LH/Low Z*
E1 (120 Ω)/LH/Low Z
T1 (100 Ω)/SH/Mat Z
E1 (75 Ω)/SH/Mat Z
E1 (120 Ω)/SH/Mat Z
TX Transformer
1:2
1:2
1:1.5
1:1.5
1:1.5
RX Transformer
1:1
1:1
1:1
1:1
1:1
R1-R2
50 Ω
60 Ω
50 Ω
37.5 Ω
60 Ω
R3-R4
12.5 Ω
15 Ω
0**
0**
0**
Table 2. Transformer and Resistor Options
SH=Short Haul; LH = Long Haul; Mat Z = Matched Impedance; Low Z = Low Impedance
* Default setting from the factory; **R3-R4 are shorted by placing HDR1-HDR2 in MATZ positions.
DS211DB2
5
5 Page 
+5V
HDR12
HDR5X2
DB25F_RA
J1
1
L2
14
2 SCLK FERRITE_BEAD
15
3 SDI
L3
16
4 CS
17
FERRITE_BEAD
L4
5
18 FERRITE_BEAD
6
19
7
20
8
21
9
22
10
23
11 FERRITE_BEAD
24 L5
12 INT
25
13 SDO
L6
FERRITE_BEAD
GND
+5V
SW1
6
5
4
3
2
1
SW_DIP_6
TAOS
LLOOP
RLOOP
LBO2
LBO1
JASEL
GND
INT
CS
SDI
SCLK/LLOOP
U2
1 20
19 /G1 VCC
/G2
2
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
A8
18
Y1 17
Y2 16
Y3 15
Y4 14
Y5 13
Y6 12
Y7 11
Y8
10
GND
SN74HCT541N
GND
C15
.1UF
R9
47
100PF
C9
COG
R10 GND
GND 47
C10
100PF COG
R8
47
C8
COG 100PF
GND R7
C7 47
COG 100PF
GND
R11
47
100PF
C11
COG
GND
GND
1N4148
D6
RN1
47K
1N4148
1N4148
D8
HDR1X2
HDR10
12
HWMODE
D7
HW_RST/NLOOP
R12
S2
SW_B3W_1100
100
GND
GND +5V
U4
11 10
MC74F14N
U4
13 12
MC74F14N
GND
BNC
J2 MCLK
BNC
J5
TCLK
BNC
J6 TPOS
BNC
J7
TNEG
BNC
J8
RNEG
BNC
RPOS
J9
BNC
J12 RCLK
GND
HDR8
12
TNEG_HI
HDR9
RNEG
RPOS
RCLK
R6
4.7K
6.1760MHZ
Y1
GND
+5V
S1 +5V
1 SW
2 3 HW
4
SW_SP3T
HWCDR
GND
HDR7
GND
12
34
J18 J19
+5V GND
Z1 P6KE6V8P
L1
FERRITE_BEAD
C1
47UF
+5V
GND
4 3 2 1 28 27 26
5
MODE
6
RNEG/BPV
L802/
SDO
L801/SDI
25
24
7
RPOS/RDATA
8
RCLK
U1
CS61581
NLOOP/INT
RGND
23
22
9 XTALIN SKT_PLCC28_ECM
21
RV+
10
XTALOUT
20
RRING
11
JASEL
19
RTIP
12 13 14 15 16 17 18
TTIP
GND
LATN
TRING
HDR6
R1
49.9
C3
5
3
RRING
TP1
6
HDR5
HDR1X2
RECEIVE
J3
6
7
8
.47UF
R2
49.9
1
GND
PE_64936
T1
TP2
2
RTIP
9
10
C2
47PF
CON_RTT87
RTIP
C4
.1UF
COG
V+ JP8
HDR3
21
GND
RRING
RRING
RTIP
V+
C5
.1UF
JP9
C6
47UF
C12
R3
12.4
R4
12.4
MATZ
HDR1
12
34
LOWZ
MATZ
HDR2
21
43
LOWZ
TRING
T2 TP3
PE_65351
21
TTIP
3
TP4
65
/T-1054
.47UF
C14
.1UF
HDR4
HDR1X2
GND
U3
TRANSMIT
J3
1
2
3
4
5
CON_RTT87
TTIP
TRING
RCLK
LATN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PALCE20RA10H
U4
56
MC74F14N
U4
98
MC74F14N
C13
.1UF
VCC 14 U4
12
MC74F14N
GND 7
GND U4
34
MC74F14N
LED_555_5003
+5V
LATN1
54
LATN2
63
LOS
72
NLOOP
81
D1
Figure 4. CDB61581 Evaluation Board Schematic
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CDB61581.PDF ] | |
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