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PDF FS6131-01 Data sheet ( Hoja de datos )
| Número de pieza | FS6131-01 | |
| Descripción | Programmable Line Lock Clock Generator IC | |
| Fabricantes | AMI | |
| Logotipo |  |
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FS6131-01
Programmable Line Lock Clock Generator IC
1.0 Features
• Complete programmable control via I2Cä-bus
• Selectable CMOS or PECL compatible outputs
• External feedback loop capability allows genlocking
• Tunable VCXO loop for jitter attenuation
• Commercial (FS6131-01) and industrial (FS6131-01i)
temperature versions available
3.0 Applications
• Frequency Synthesis
• Line-Locked and Genlock Applications
• Clock Multiplication
• Telecom Jitter Attenuation
Figure 1: Pin Configuration
2.0 Description
The FS6131-01 is a monolithic CMOS clock genera-
tor/regenerator IC designed to minimize cost and compo-
nent count in a variety of electronic systems. Via the I2C-
bus interface, the FS6131-01 can be adapted to many
clock generation requirements.
The ability to tune the on-board voltage-controlled crystal
oscillator (VCXO), the length of the Reference and Feed-
back Dividers, their granularity, and the flexibility of the
Post Divider make the FS6131-01 the most flexible
stand-alone phase-locked loop (PLL) clock generator
available.
SCL 1
SDA 2
ADDR 3
VSS 4
XIN 5
XOUT 6
XTUNE 7
VDD 8
16 CLKN
15 CLKP
14 VDD
13 FBK
12 REF
11 VSS
10 EXTLF
9 LOCK/IPRG
16-pin 0.150" SOIC
Figure 2: Block Diagram
XTUNE
(optional)
XIN
XOUT
(optional)
REF
FBK
ADDR
SCL
SDA
XCT[3:0],
XLVTEN
VCXO
Control
ROM
VCXO
Divider
REFDIV[11:0]
0 (fREF)
1
REFDSRC
Reference
Divider
(NR)
PDREF
0
1
1
0
PDFBK
I2C
Interface
Registers
XLROM[2:0]
XLPDEN,
XLSWAP
CRYSTAL LOOP
XLCP[1:0]
Phase-
Frequency
Detector
UP
Charge
Pump
DOWN
MLCP[1:0]
VCOSPD,
OSCTYPE
LFTC
Internal
Loop
Filter
01
EXTLF
STAT[1:0]
CLF
CLP
RLF
EXTLF
(optional)
Lock
CMOS
1
Detect
POST3[1:0]
POST2[1:0]
GBL
POST1[1:0]
0
LOCK/
IPRG
(optional)
Phase-
Frequency
Detector
UP
Charge
Pump
DOWN
Voltage
Controlled
Oscillator
Feedback
Divider (NF)
FBKDIV[13:0]
11
01
10
00
FBKDSRC[1:0]
11
01
00
10
Clock
Gobbler
OUTMUX[1:0]
(fVCO)
Post
Divider
(NPx)
CMOS/PECL
Output
MAIN LOOP
FS6131
CLKP
(fCLK)
CLKN
I2C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail
specifications as may be required to permit improvements in the design of its products.
1 page  
FS6131-01
Programmable Line Lock Clock Generator IC
To enter this mode, set STAT[1] to one and clear
STAT[0] to zero. If the CMOS bit is set to one, the
LOCK/IPRG pin can display the flag. The flag is always
available under software control by reading back the
STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4 Feedback Divider Monitoring
The Feedback Divider clock can be brought out the
LOCK/IPRG pin independent of the output clock to allow
monitoring of the Feedback Divider clock. To enter this
mode, set both the STAT[1] and STAT[0] bits to one. The
CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
4.3 Loop Gain Analysis
For applications where an external loop filter is required,
the following analysis example can be used to determine
loop gain and stability.
The loop gain of a PLL is the product of all of the gains
within the loop.
Establish the basic operating parameters:
Set the charge pump current: I chgpump = 10µA
Set the loop filter values:
RLF = 15kΩ
C1 = 0.015µF
C2 = 220 pF
Set the VCO gain (VCOSPD): AVCO = 230MHz /V
Set the Feedback Divider:
N F = 3500
Set the Reference frequency (at the input to the Phase
Detector:
f REF = 20kHz
The transfer function of the Phase Detector and Charge
Pump combination is (in A/rad):
K PD
=
I chgpump
2π
The transfer function of the loop filter is (in V/A):
K LF
(s)
=
sC2
çæ
+ç
ççè
1
1
÷ö
÷
RLF + çèæ 1sC1 ÷øö ÷÷ø
The VCO transfer function (in rad/s, and accounting for
the phase integration that occurs in the VCO) is:
KVCO
(s)
=
2πAVCO
1
s
The transfer function of the Feedback Divider is:
KF
=
1
NF
Finally, the sampling effect that occurs in the Phase De-
tector is accounted for by:
K SAMP (s)
=
çæ1 −
ç
çè
e −çèæ s
s
f REF
÷øö
÷ö
÷
÷ø
f REF
The loop gain of the PLL is:
K LOOP (s) = K PD K LF (s)KVCO (s)K F K SAMP (s)
Figure 8: Loop Gain vs. Frequency
100
10
1
0.1
0.01
0.1kHz
1kHz
10kHz
Frequency (fi)
100kHz
5
5 Page 
FS6131-01
Programmable Line Lock Clock Generator IC
Figure 13: Random Register Write Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Acknowledge
START
Command
WRITE Command
From bus host
to device
From device
to bus host
STOP Condition
Acknowledge
Figure 14: Random Register Read Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
START
Command
WRITE Command
From bus host
to device
7-bit Receive
Device Address
Repeat START
Acknowledge
From device
to bus host
Data
Acknowledge
READ Command
STOP Condition
NO Acknowledge
Figure 15: Sequential Register Write Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A DATA A DATA A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Acknowledge
START
Command
WRITE Command
From bus host
to device
From device
to bus host
Data
Acknowledge
Figure 16: Sequential Register Read Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A
DATA
Acknowledge
Data
Acknowledge
STOP Command
A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
START
Command
WRITE Command
From bus host
to device
7-bit Receive
Device Address
Repeat START
Acknowledge
From device
to bus host
Data
Acknowledge
READ Command
11
Acknowledge
Data
NO Acknowledge
STOP Command
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FS6131-01.PDF ] | |
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