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PDF 83C196MC Data sheet ( Hoja de datos )

Número de pieza 83C196MC
Descripción INDUSTRIAL MOTOR CONTROL MICROCONTROLLER
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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8XC196MC
INDUSTRIAL MOTOR CONTROL
MICROCONTROLLER
87C196MC 16 Kbytes of On-Chip OTPROM
87C196MC ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM
80C196MC ROMless
Y High-Performance CHMOS 16-Bit CPU
Y 16 Kbytes of On-Chip OTPROM
Factory-Programmed OTPROM
Y 488 bytes of On-Chip Register RAM
Y Register to Register Architecture
Y Up to 53 I O Lines
Y Peripheral Transaction Server (PTS)
with 11 Prioritized Sources
Y Event Processor Array (EPA)
4 High Speed Capture Compare
Modules
4 High Speed Compare Modules
Y Extended Temperature Standard
Y Two 16-Bit Timers with Quadrature
Decoder Input
Y 3-Phase Complementary Waveform
Generator
Y 13 Channel 8 10-Bit A D with Sample
Hold with Zero Offset Adjustment H W
Y 14 Prioritized Interrupt Sources
Y Flexible 8- 16-Bit External Bus
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y Idle and Power Down Modes
The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush-
less motors The 8XC196MC is based on Intel’s MCS 96 16-bit microcontroller architecture and is manufac-
tured with Intel’s CHMOS process
The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor
control applications This peripheral allows for pulse width modulation three phase sine wave generation with
minimal CPU intervention It generates 3 complementary non-overlapping PWM pulses with resolutions of
0 125 ms (edge trigger) or 0 250 ms (centered)
The 8XC196MC has 16 Kbytes on-chip OTPROM ROM and 488 bytes of on-chip RAM It is available in three
packages PLCC (84-L) SDIP (64-L) and EIAJ QFP (80-L)
Note that the 64-L SDIP package does not include P1 4 P2 7 P5 1 and the CLKOUT pins
Operational characteristics are guaranteed over the temperature range of b40 C to a85 C
The 87C196MC contains 16 Kbytes on-chip OTPROM The 83C196MC contains 16 Kbytes on-chip ROM All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted
OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package
and cannot be erased It is user programmable
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
April 1994
Order Number 270946-005

1 page




83C196MC pdf
8XC196MC
NOTE
NC means No Connect Do not connect these pins
Figure 3 84-Lead PLCC Package
270946 – 3
5

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83C196MC arduino
8XC196MC
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time The characters in a pair indicate a signal and its
condition respectively Symbols represent the time between the two signal condition points
Conditions
H High
L Low
V Valid
X No Longer Valid
Z Floating
Signals
A Address
B BHE
C CLKOUT
D DATA
G Buswidth
H HOLD
HA HLDA
L ALE ADV
BR BREQ
R RD
W WR WRH WRL
X XTAL1
Y READY
Q Data Out
AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz
The system must meet the following specifications to work with the 87C196MC
Symbol
Parameter
Min Max
FXTAL
TOSC
TAVYV
TLLYV
TYLYH
TCLYX
TLLYX
TAVGV
TLLGV
TCLGX
TAVDV
TRLDV
TCLDV
TRHDZ
TRXDX
Frequency on XTAL1
1 FXTAL
Address Valid to READY Setup
ALE Low to READY Setup
Not READY Time
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to BUSWIDTH Setup
ALE Low to BUSWIDTH Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
8 16
62 5 125
2 TOSC b 75
TOSC b 70
No Upper Limit
0
TOSC b 15
0
TOSC b 30
2 TOSC b 40
2 TOSC b 75
TOSC b 60
3 TOSC b 55
TOSC b 22
TOSC b 50
TOSC
0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3
4
1
1
4
2
2
NOTES
1 If Max is exceeded additional wait states will occur
2 If wait states are used add 2 TOSC N where N e number of wait states
3 Testing performed at 8 MHz However the device is static by design and will typically operate below 1 Hz
4 These timings are included for compatibility with older b90 and BH products They should not be used for newer high-
speed designs
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