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PDF CDB5345 Data sheet ( Hoja de datos )
| Número de pieza | CDB5345 | |
| Descripción | Evaluation Board | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CDB5345
Evaluation Board for CS5345
Features
z Single-ended Analog Inputs
z Single-ended Analog Outputs
z CS8406 S/PDIF Digital Audio Transmitter
z Header for Optional External Software
Configuration of CS5345
z Header for External PCM Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z Demonstrates Recommended Layout and
Grounding Arrangements
z Windows® Compatible Software Interface
to Configure CS5345 and Inter-board
Connections
ORDERING INFORMATION
CDB5345
Evaluation Board
Description
The CDB5345 evaluation board is an excellent means
for evaluating the CS5345 ADC. Evaluation requires an
analog signal source and analog/digital analyzer, and
power supplies. A Windows® PC compatible computer
must be used to evaluate the CS5345.
System timing for the I²S, Left-Justified and Right-Justi-
fied interface formats can be provided by the CS5345,
the CS8406, or by a PCM I/O stake header with an ex-
ternal source connected.
RCA phono jacks are provided for the CS5345 analog in-
puts and outputs. Digital data input is available via RCA
phono or optical connectors to the CS8406.
The Windows® software provides a GUI to make config-
uration of the CDB5345 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS5345 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
I
Passive Input Filter
Active Input Filter
Microphone Input
M
U
X
CS5345
Active Output Filter
Test Points
Master Clock
Canned
Oscillator
Control Port Interface
FPGA
Sub-clocks and Data
Header
CS8406
Cirrus Logic, Inc.
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
FEB ‘05
DS658DB1
1 page  
CDB5345
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with
a 12.2880 MHz crystal oscillator populated.
1.7 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the headers J10, and
J17.
The 8-pin, 2 row header, J10, provides access to the serial audio signals required to interface to the serial
audio port of the CS5345 with a DSP (see Figure 10 on page 22).
The direction of the signals on header J10 can be configured using the controls located within the Board
Controls group box on the CDB5345 Controls tab in the provided GUI software.
The 15-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I2C control signals by simply
removing all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable
to the “EXTERNAL CONTROL” position. A single “GND” row for the ribbon cable’s ground connection is pro-
vided to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user
choose to use the CDB for the I2C power rail.
1.8 Analog Inputs
RCA connectors supply the CS5345 analog inputs through single-ended, unity gain, active or passive cir-
cuits. Refer to the CS5345 data sheet for the ADC full-scale level.
A 4-pin CD-ROM type header is provided for easily connecting the analog outputs from a CD-ROM drive to
the analog inputs of the CS5345.
1.9 Analog Outputs
The CS5345 PGA analog outputs are routed through a two-pole active filter. The output of the filter is con-
nected to RCA jacks for easy evaluation.
1.10
Serial Control Port
A graphical user interface is included with the CDB5345 to allow easy manipulation of the registers in the
CS5345, CS8406, and FPGA. See the device-specific data sheets for the CS5345 and CD8406 internal reg-
ister descriptions. The internal register map for the FPGA is located in section 4 on page 10.
Connecting a cable to the RS-232 connector (J42) and launching the Cirrus Logic FlexGUI software (Flex-
Loader.exe) will enable the CDB5345.
Refer to “PC Software Control” on page 7 for a description of the Graphical User Interface (GUI).
1.11 USB Control Port
The USB control port connector (J37) is currently unavailable.
DS658DB1
5
5 Page 
5. FPGA REGISTER DESCRIPTION
CDB5345
5.1 CODE REVISION ID - ADDRESS 01H
7
Rev7
6
Rev6
5
Rev5
4
Rev4
3
Rev3
2
Rev2
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
1
Rev1
0
Rev0
5.2 MCLK SOURCE CONTROL - ADDRESS 02H
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
MCLK
5.2.1 MCLK SOURCE (BIT 0)
Default = 0
Function:
This bit selects the source of the CS5345 MCLK signal. Table 1 shows the available settings.
Table 1. MCLK Source
MCLK
0
1
MCLK Source
Canned Oscillator
M1 position on PCM1 I/O Header
DS658DB1
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CDB5345.PDF ] | |
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