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PDF CDB4351 Data sheet ( Hoja de datos )

Número de pieza CDB4351
Descripción STEREO DAC
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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CS4351
192 kHz Stereo DAC with 2 Vrms Line Out
Features
z Multi-bit Delta-Sigma Modulator
z 24-Bit Conversion
z Up to 192 kHz Sample Rates
z 112 dB Dynamic Range
z -100 dB THD+N
z +3.3 V, +9 to 12 V, and VL Power Supplies
z 2 Vrms Output into 5 kAC Load
z Digital Volume Control with Soft Ramp
– 119 dB Attenuation
– 1/2 dB Step Size
– Zero Crossing Click-Free Transitions
z ATAPI Mixing
z Low Clock Jitter Sensitivity
z Popguard Technology® for Control of Clicks
and Pops
I
Description
The CS4351 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-em-
phasis, volume control, channel mixing, analog filtering,
and on-chip 2 Vrms line level driver. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature, high toler-
ance to clock jitter, and a minimal set of external
components.
These features are ideal for cost-sensitive, 2-channel
audio systems including DVD players, A/V receivers,
set-top boxes, digital TVs and VCRs, mini-component
systems, and mixing consoles.
ORDERING INFORMATION
CS4351-CZ
-10 to 70 °C 20-pin TSSOP
CS4351-CZZ, Lead Free -10 to 70 °C 20-pin TSSOP
CDB4351
Evaluation Board
1.8 V to 3.3V
Hardware or I2C/SPI
Control Data
Reset
Serial Audio Input
3.3 V
Register/Hardware
Configuration
PCM
Serial
Interface
Interpolation
Filter with
Volume Control
Interpolation
Filter with
Volume Control
Multibit
∆Σ Modulator
Multibit
∆Σ Modulator
Auto Speed Mode
Detect
9 V to 12 V
DAC
Amp
+
Filter
2 Vrms Line Level
Left Channel Output
DAC
Amp
+
Filter
2 Vrms Line Level
Right Channel
Output
Internal Voltage
Reference
External
Mute
Control
Left and Right
Mute Controls
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
Sep ‘04
DS566PP2

1 page




CDB4351 pdf
CS4351
LIST OF TABLES
Table 1. Revision History ...............................................................................................................2
Table 2. CS4351 Auto-Detect .......................................................................................................16
Table 3. CS4351 Mode Select ......................................................................................................16
Table 4. Single-Speed Mode Standard Frequencies ....................................................................17
Table 5. Double-Speed Mode Standard Frequencies...................................................................17
Table 6. Quad-Speed Mode Standard Frequencies .....................................................................17
Table 7. Digital Interface Format - Stand-Alone Mode..................................................................18
Table 8. Digital Interface Formats .................................................................................................27
Table 9. ATAPI Decode ................................................................................................................29
Table 10. Example Digital Volume Settings ..................................................................................31
DS566PP2
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CDB4351 arduino
CS4351
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (Manual selection)
Input Sample Rate (Auto selection)
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Symbol
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
Fs
Fs
Fs
Single Speed Mode
Double Speed Mode
Quad Speed Mode
tsclkl
tsclkh
tsclkw
tsclkw
tsclkw
tslrd
tslrs
tsdlrs
tsdh
Min
1.024
45
4
50
100
4
84
170
40
20
20
(---1---2----81---)---F----s-
(---6---4--1--)--F----s--
M------C--2---L---K---
20
20
20
20
Max Units
51.2
MHz
55 %
50 kHz
100 kHz
200 kHz
50 kHz
100 kHz
200 kHz
60 %
- ns
- ns
--
--
--
- ns
- ns
- ns
- ns
LRCK
SCLK
SDATA
t slrd
t sdlrs
t slrs t sclkh
t sclkl
t sdh
Figure 1. Serial Input Timing
DS566PP2
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