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PDF KL5KUSB201 Data sheet ( Hoja de datos )

Número de pieza KL5KUSB201
Descripción USB2.0 Compliant Transceiver Chip
Fabricantes Kawasaki 
Logotipo Kawasaki Logotipo



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Kawasaki USB device
KL5KUSB201
Datasheet (digest) rev 1.1E page 1/21
KL5KUSB 201
USB2.0 Compliant Transceiver Chip
Datasheet (Digest)
Rev 1. 1E (2002.4.8)
Kawasaki Microelectronics Inc.
Kawasaki LSI Inc.
Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

1 page




KL5KUSB201 pdf
Kawasaki USB device
KL5KUSB201
Datasheet (digest) rev 1.1E page 5/21
1. Overview
Kawasaki Microelectronics Inc. and Kawasaki LSI Inc. introduce KL5KUSB201 LSI,
which is designed based on USB Specification revision 2.0 and operates as both
USB2.0 High Speed and Full Speed transceiver chip. It has two modes – UTMI
Specification compatible mode and Kawasaki Original mode. In Kawasaki Original
mode, the LSI has several convenient function such as automatic CRC generation and
verification, transmit packet abortion and automatic test packet generation for High
Speed Signal Quality test. The LSI is recognized as USB2.0 PHY chip and customers
are able to build up USB2.0 compliant device system with their logic and PHY control /
endpoint buffer function (SIE), which is available by Kawasaki or other IP vendor.
Figure 1. KL5KUSB201 Image
1.1 Chip Functionality
KL5KUSB201 Fucntionality is summarized below.
1. HS Chirp Signal Generation and Detection
2. Support for both High Speed (480Mbit/sec) and Full Speed (12Mbit/sec)
3. For received packet, phase lock, buffering, SYNC detection, NRZI decode, bit
un-stuffing, CRC error detection (optional), serial to parallel conversion are
performed. 16bit data is drived on SIE bus
4.For packet transmission, parallel 16bit data is received, serialized, CRC
Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

5 Page





KL5KUSB201 arduino
Kawasaki USB device
KL5KUSB201
Datasheet (digest) rev 1.1E page 11/21
6. Signal Description
Table 6 describes signal function description and related name in UTMI.
Table 6 Signal Description
No Signal Name I/O
Description
UTMI
name
1 REXT
O Reference bias current pin. Connect to GND via
--
external resistor Rext.
2 HSDP
I/O High Speed DP pin. Connect to USB Bus D+.
DP
3 HSDM
I/O High Speed DM pin. Connect to USB Bus D-.
DM
4 RPU_ENA
O Pull up resister source pin. Connect to external
--
resistor Rpu, which is tied to USB bus D+.
RPU_ENA becomes 3-state in High Speed
operation.
5 FSDP
I/O Full Speed DP pin. Connect to USB Bus D+ via (DP)
termination resistor Rs.
6 FSDM
I/O Full Speed DM pin. Connect to USB Bus D- via (DM)
termination resistor Rs.
7 XIN
I 48MHz clock input pin. Connect to crystal oscillator
--
or crystal oscillation circuit.
8 XOUT
O 48MHz clock output pin for crystal oscillation circuit.
--
9 FS_HSN
I USB bus speed control pin.
XcvrSelect
10 PU_SE0N
I Termination control pin. With FS_HSN and MODE, TermSelect
LSI operation mode is selected.
11 CKOUT
O SIE bus clock pin. Frequency is 30MHz.
CLK
12 RXACT
O USB packet received signal.
RXActive
13 RXVLD
O SIE bus out data valid signal. Active H.
RXValid
(RXValidH)
14 CRCERR
O CRC error detection signal. Active when CRC logic
--
is enabled.
15 RXERR
O Receive error detection signal. RX error indicator RXError
except for CRC error.
16 TXACT
I USB bus data transmit control signal. SIE bus TXValid
switches from output to input when active.
(TXValidH)
17 TXRDY
O SIE input data ready signal. Valid when TXACT is TXReady
active.
18 CRCACT
I CRC detection logic enable signal. Also used for
--
data transmit abortion.
19 SIE_DAT[15:0] I/O 16bit parallel 3-state SIE data bus. Synchronized Data15-8,
with CKOUT. Data direction is input when TXACT Data7-0
assertion. Default direction is output.
20 WDVLD
I/O SIE data width indication signal. If last SIE data is a ValidH
byte data, WDVLD is asserted.
21 RSTN
I Hardreset signal. Active L. Assertion required when RST
power on and USB reset recognition.
(assert H)
Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

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