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PDF KL5KUSB101 Data sheet ( Hoja de datos )
| Número de pieza | KL5KUSB101 | |
| Descripción | USB to Ethernet Controller | |
| Fabricantes | Kawasaki | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KL5KUSB101 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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KL5KUSB101
General Description
USB to Ethernet Controller
The Kawasaki KL5KUSB101 Controller is a unique single chip solution to interface peripheral
devices to the Universal Serial Bus (USB) and Ethernet. The KL5KUSB101 has been specifically
designed to provide a simple solution to communicate with Ethernet applications as well as other
USB peripheral devices. This has been accomplished by its highly integrated functionality. The
USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator,
Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and
SPORT Interface. The SIE (Serial Interface Engine) is fully compatible with the USB specification.
This USB to Ethernet controller is ideal for LAN (Local Area Network), HAN (Home Area
Network), Cable Modem, Set Top Boxes, or Mobile Networking applications.
Features
• Advanced 16 Bit processor for USB transaction
processing and control data processing
• USB interface ver. 1.0/1.1 compliant
• Transceivers and SIE (Serial Interface Engine)
• Internal Clock Generation
• Utilizes low cost external crystal circuitry
• 1.5K x 16 Internal RAM buffer
• Serial Interface for external EEPROM
Block Diagram
• Watchdog timer
• Fully IEEE 802.3 compliant 10 Mbit/sec
Ethernet MAC Layer. Interfaces serially of
an external ENDEC PHY.
• UART
• External memory interface
• 100 pin QFP and LQFP package
Txd
Rxd UART
CK EEPROM
Serial Interface
DIO
2
INT 1-0
IRQ
8 10Mb/s
Ethernet
Interface
Timer 0
Timer 1
RAM
(3KB)
Mask ROM
(8KB)
16 Bit
Processor
Watchdog
Timer
SRAM Interface
16 Bit Address / Data Bus
Serial
Interface
Engine
Clock
Generator
USB Interface
Data -
Data +
A15-0
D15-0
Cntrl .
X1
X2
Ver. 2.4
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
1
1 page  
Pin #
QFP
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin #
LQFP
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
KL5KUSB101
I/O Pin Name
USB to Ethernet Controller
Description
IN
OUT
OUT
N/C
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
GND
nXRD
nXWR
nXROMSEL
nRESET
nTST
XA_1
XA_2
XA_3
XA_4
XA_5
XA_6
XA_7
XA_8
XA_9
XA_10
XA_11
XA_12
XA_13
XD_0
XD_1
XD_2
XD_3
XD_4
XD_5
XD_6
XD_7
XD_8
XD_9
XD_10
XD_11
IGND
XD_12
XD_13
OGND
XD_14
GND
External Memory Read (Active low)
External Memory Write (Active low)
External ROM CS, active LO
Reset Pin
Test Pin, Disconnect for Normal Operation
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Address Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
External Data Pins
GND
External Data Pins
External Data Pins
GND
External Data Pins
Ver. 2.4
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
5
5 Page 
KL5KUSB101
USB to Ethernet Controller
Table 3.1.2 PHY SQE Transmit AC Characteristics (over recommended range)
Symbol
Parameter
Min Typ Max Unit Not
e
Tcol PHYCOL assert delay – – 1.6 us –
from PHYTEN fall
Tpco PHYCOL low width
0.5 –
– us –
3.2 U2E to PHY receive
Figure 3.2.1 U2E from PHY Receive AC Timing
PHYRCLK
(IN)
Trck
Tscd
Trch
Trcl
Thcd
PHYCD
(IN)
PHYRXD
(IN)
Tsrd
first
Thrd
last
Table 3.2.1 Receive from PHY AC Characteristics (over recommended range)
Symbol
Parameter
Min Typ Max Unit Not
e
Trck PHYRCLK period
– 100 – ns 1
Frck PHYRCLK frequency – 10 – MH 1
z
Trch PHYRCLK high width – 50 – ns –
Trcl PHYRCLK low width – 50 – ns –
Tscd PHYCD setup time
to PHYRCLK rise
20 –
– ns –
Thcd PHYCD hold time
from PHYTCLK rise
10 –
– ns –
Tsrd
PHYRXD setup time
to PHYRCLK fall
20 –
– ns –
Thrd
PHYRXD hold time
from PHYRCLK fall
10 –
– ns –
Note: 1) PHY generates the 10MHz clock.
Ver. 2.4
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet KL5KUSB101.PDF ] | |
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