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PDF ICS557-05A Data sheet ( Hoja de datos )
| Número de pieza | ICS557-05A | |
| Descripción | Quad Differential PCI-Express Clock Source | |
| Fabricantes | ICST | |
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ICS557-05A
Quad Differential PCI-Express Clock Source
Description
The ICS557-05A is a spread-spectrum clock generator
that supports PCI-Express requirements. It is used in
PC or embedded systems to substantially reduce
electro-magnetic interference (EMI). The device
provides four differential HCSL or LVDS high-frequency
outputs with spread spectrum capability. The output
frequency and spread type are selectable using
external pins.
Features
• Packaged in 20-pin TSSOP
• Available in Pb (lead) free package
• Supports PCI-Express applications
• Four differential spread spectrum clock outputs
• Spread spectrum for EMI reduction
• Uses external 25 MHz clock or crystal input
• Power down pin turns off chip
• OE control tri-states outputs
• Spread and frequency selection via external pins
• Spread Bypass option available
• Industrial temperature range available
Block Diagram
VDD
2
PD OE
3
SEL[2:0]
25 MHz
crystal or
clock
X1
X2
Optional tuning crystal
capacitors
Spread
Spectrum/
Output
clock
selection
Clock
Oscillator
Spread
Spectrum
Circuitry
PLL Clock
Synthesis
2
GND
Rr(IREF)
CLKOUTA
CLKOUTA
CLKOUTB
CLKOUTB
CLKOUTC
CLKOUTC
CLKOUTD
CLKOUTD
MDS 557-05A E
1
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
Output Structures
IREF
=2.3 mA
6*IREF
ICS557-05A
Quad Differential PCI-Express Clock Source
See Output Termination
RR 475Ω Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the
ICS557-05A.This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 557-05A E
5
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page 
ICS557-05A
Quad Differential PCI-Express Clock Source
Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
20
INDEX
AREA
12
D
A2
e
b
Millimeters
Inches*
E1 E
A
Symbol
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
Min Max
1.20
0.05 0.15
0.80 1.05
0.19 0.30
0.09 0.20
6.40 6.60
6.40 BASIC
4.30 4.50
0.65 Basic
0.45 0.75
0° 8°
-- 0.10
Min Max
0.047
0.002 0.006
0.032 0.041
0.007 0.012
0.0035 0.008
0.252 0.260
0.252 BASIC
0.169 0.177
0.0256 Basic
0.018 0.030
0° 8°
-- 0.004
*For reference only. Controlling dimensions in mm.
A1
-C-
SEATING
PLANE
aaa C
c
L
MDS 557-05A E
11
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS557-05A.PDF ] | |
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