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PDF ICS556-04 Data sheet ( Hoja de datos )

Número de pieza ICS556-04
Descripción LOW SKEW 1 TO 4 CLOCK BUFFER
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ICS556-04
LOW SKEW 1 TO 4 CLOCK BUFFER
Description
The ICS556-04 is a low-skew, crystal input compatible
clock buffer with oscillator. This device offers the lowest
skew.
See the ICS552-02 for a 1-to-8 low skew buffer. For
more than eight outputs see the MK74CBxxx BuffaloTM
series of clock drivers.
ICS makes many non-PLL and PLL-based low-skew
output devices. Contact ICS for all of your clocking
needs.
Features
Extremely low-skew outputs (50 ps maximum)
Packaged in 8-pin SOIC
Operating voltages of 2.5 to 5.0 V
Low-power CMOS technology
Industrial temperature range
Available in Pb (lead) free package
Block Diagram
5 to 27 MHz
Crystal or clock
X1/ICLK
X2
Crystal
Oscillator/
Buffer
Optional crystal
capacitors
Q0
Q1
Q2
Q3
MDS 556-04 C
1
Revision 030905
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

1 page




ICS556-04 pdf
ICS556-04
LOW SKEW 1 TO 4 CLOCK BUFFER
AC Electrical Characteristics
VDD = 2.5 V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Input Frequency
5
Output Rise Time
Output Fall Time
Output to output skew
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
Rising edges at VDD/2
Duty Cycle
Measured at VDD/2
45
Typ.
1.8
1.8
0
50
Max.
27
2.5
2.5
50
55
Units
MHz
ns
ns
ps
%
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Input Frequency
5
Output Rise Time
Output Fall Time
Output to output skew
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
Rising edges at VDD/2
Duty Cycle
Measured at VDD/2
45
Phase Noise at 1MHz from
carrier
Clock Jitter RMS 1KHz to 1MHz
Typ.
0.6
0.6
0
50
-125
Max. Units
27 MHz
1.0 ns
1.0 ns
50 ps
55 %
dBc/Hz
6 ps
VDD = 5 V ±5%, Ambient Temperature -40 to +85 °C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Input Frequency
5
Output Rise Time
Output Fall Time
Output to output skew
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
Rising edges at VDD/2
Duty Cycle
Measured at VDD/2
45
Notes: 1. Between any two outputs with equal loading.
Typ.
0.3
0.3
0
50
Max.
27
0.7
0.7
50
55
Units
MHz
ns
ns
ps
%
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Min.
Typ.
150
140
120
40
Max. Units
°C/W
°C/W
°C/W
°C/W
MDS 556-04 C
5
Revision 030905
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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