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PDF FS6261-01 Data sheet ( Hoja de datos )
| Número de pieza | FS6261-01 | |
| Descripción | Motherboard Clock Generator IC | |
| Fabricantes | AMI | |
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January 2000
1.0 Features
• Generates clocks required for Intel® i820 based
desktop and workstation systems, including:
♦ Four enabled 2.5V 133/100MHz CPU Front Side
Bus (FSB) clocks
♦ Two 2.5V CPU/2 clocks for synchronous memory
♦ Seven enabled 3.3V PCI bus clocks and one
free-running PCI clock
♦ Four enabled 3.3V 66MHz AGP clocks
♦ Three 2.5V 16.67MHz APIC bus clocks
♦ Two 3.3V 14.318MHz REF clocks
♦ One 3.3V 48MHz USB clock
• CPU clock cycle – cycle jitter < 150ps p-p
• Non-linear spread-spectrum modulation
(-0.5% at 31.5kHz)
• Supports test mode and tristate output control
• Separate CPU-enable, PCI-enable and power-down
inputs with glitch-free stop clock controls on all clocks
for clock control and power management
Figure 1: Block Diagram
XIN
XOUT
SEL_0:1
SS_EN#
SEL_133/100#
PWR_DWN#
CPU_STOP#
PCI_STOP#
Crystal
Oscillator
PLL
÷2
delay
÷6 or
÷8
VDD_R
REF_0:1
VSS_R
VDD_C2
CPU/2_0:1
VSS_C2
VDD_A
APIC_0:2
VSS_A
VDD_C
CPU_0:3
VSS_C
(2.5V outputs)
delay
÷1½
or ÷2
delay
÷3 or
÷4
VDD_66
CK66_0:3
VSS_66
VDD_P
PCI_F
PCI_1:7
VSS_P
PLL
÷3 or
÷4
VDD_48
CK48
VSS_48
FS6261-01
2.0 Description
The FS6261-01 is a CMOS clock generator IC designed
for high-speed motherboard applications. Two different
frequencies can be selected for the CPU clocks via two
SEL pins. Glitch-free stop clock control of the CPU, AGP
(66MHz) and PCI clocks is provided. A low current
power-down mode is available for mobile applications.
Separate clock buffers provide for a 2.5V voltage range
on the CPU_0:3, CPU/2_0:1 and APIC_0:2 clocks.
Figure 2: Pin Configuration
VSS_R 1
REF_0 2
REF_1 3
VDD_R 4
XIN 5
XOUT 6
VSS_P 7
PCI_F 8
PCI_1 9
VDD_P 10
PCI_2 11
PCI_3 12
VSS_P 13
PCI_4 14
PCI_5 15
VDD_P 16
PCI_6 17
PCI_7 18
VSS_P 19
VSS_66 20
CK66_0 21
CK66_1 22
VDD_66 23
VSS_66 24
CK66_2 25
CK66_3 26
VDD_66 27
SEL133/100# 28
56 VDD_A
55 APIC_2
54 APIC_1
53 APIC_0
52 VSS_A
51 VDD_C2
50 CPU/2_1
49 CPU/2_0
48 VSS_C2
47 VDD_C
46 CPU_3
45 CPU_2
44 VSS_C
43 VDD_C
42 CPU_1
41 CPU_0
40 VSS_C
39 VDD
38 VSS
37 PCI_STOP#
36 CPU_STOP#
35 PWR_DWN#
34 SS_EN#
33 SEL_1
32 SEL_0
31 VDD_48
30 CK48
29 VSS_48
56-pin SSOP
Table 1: CPU/PCI Frequency Selection
SEL_133/100#
0
0
0
0
1
1
1
1
SEL_1
0
0
1
1
0
0
1
1
SEL_0
0
1
0
1
0
1
0
1
CPU (MHz)
tristate
(reserved)
100
100
XIN/2
(reserved)
133
133
PCI (MHz)
tristate
(reserved)
33.33
33.33
XIN/6
(reserved)
33.33
33.33
Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc.
reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Figure 2: CPU_STOP# Timing
CPU_
STOP#
PCI_F
CPU
(133MHz)
CPU
(100MHz)
Figure 3: PCI_STOP# Timing
PCI_
STOP#
PCI_F
PCI_1:7
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Figure 4: PWR_DWN# Timing
PWR_
DWN#
PCI_F
PCI_1:7
CPU
(133MHz)
CPU
(100MHz)
VCO
Crystal
Oscillator
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
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Table 9: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
133MHz
MIN. TYP. MAX.
100MHz
MIN. TYP. MAX.
UNITS
Overall
Spread Spectrum Modulation
Frequency *
fm SS_EN# low
31.5
31.5 kHz
Spread Spectrum Modulation Index* δm SS_EN# low
-0.5 -0.5
CPU @ 1.25V, CL=20pF to CK66 @
1.5V, CL=30pF (rising edges)
0
0.3 1.5
0
0.4 1.5
Clock Offset
tpd
CK66 @ 1.5V, CL=30pF to PCI @
1.5V, CL=30pF (rising edges)
1.5 2.9 4.0 1.5 3.1 4.0
CPU @ 1.25V, CL=20pF to APIC @
1.25V, CL=20pF (rising edges)
1.5
2.3
4.0
1.5
3.3
4.0
Tristate Enable Delay *
tDZL, tDZH SEL_0:1 and SEL_133/100#=0
1.0
10 1.0
10
Tristate Disable Delay *
tDZL, tDZH SEL_0:1 and SEL_133/100#=0
1.0
10 1.0
10
Clock Stabilization (on power-up) *
tSTB via PWR_DWN#
3.0 3.0
%
ns
ns
ns
ms
APIC_0:2 Clock Output (2.5V Type 1 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45 50 55 45 50 55
%
Clock Skew *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
tskw
tj(LT)
tj(∆P)
tr min
tr max
tf min
tf max
APIC to APIC @ 1.25V, CL=20pF
On rising edges 500µs apart at 1.25V
relative to an ideal clock, CL=20pF, all
PLLs active
From rising edge to rising edge at
1.25V, CL=20pF, all PLLs active
Measured @ 0.4V – 2.0V; CL=10pF
Measured @ 0.4V – 2.0V; CL=20pF
Measured @ 2.0V – 0.4V; CL=10pF
Measured @ 2.0V – 0.4V; CL=20pF
-70
204
82
1.2
1.5
1.8
2.1
-70
122 ps
88 ps
1.2
ns
1.5
1.5
ns
1.8
CPU/2_0:1 Clock Outputs (2.5V Type 1 Clock Buffer)
Duty Cycle *
Clock Skew *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
dt
tskw
tj(LT)
tj(∆P)
tr min
tr max
tf min
tf max
Ratio of high pulse width to one
clock period, measured at 1.5V
45 52 55
CPU/2 to CPU/2 @ 1.25V, CL=20pF
+10
On rising edges 500µs apart at
1.25V relative to an ideal clock,
CL=20pF, all PLLs active
136
From rising edge to rising edge at
1.25V, CL=20pF, all PLLs active
108
Measured @ 0.4V – 2.0V; CL=10pF
0.9
Measured @ 0.4V – 2.0V; CL=20pF
1.1
Measured @ 2.0V – 0.4V; CL=10pF
1.0
Measured @ 2.0V – 0.4V; CL=20pF
1.2
45 52 55
+10
122
112
0.8
1.1
1.0
1.2
%
ps
ps
ns
ns
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11 Page | ||
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| PDF Descargar | [ Datasheet FS6261-01.PDF ] | |
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