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PDF AZ10ELT20 Data sheet ( Hoja de datos )

Número de pieza AZ10ELT20
Descripción CMOS/TTL to Differential PECL Translator
Fabricantes Arizona 
Logotipo Arizona Logotipo



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ARIZONA MICROTEK, INC.
AZ10ELT20
AZ100ELT20
CMOS/TTL to Differential PECL Translator
FEATURES
0.5ns Typical Propagation Delay
Differential PECL Outputs
Flow Through Pinouts
Operating Range of +3.0V to +5.5V
Direct Replacement for ON Semi
MC100ELT20 & Micrel SY89329V
Available in 2x2 and 3x3 mm MLP
Packages
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER MARKING NOTES
MLP 8 (2x2x0.75) AZ100ELT20N
T0
<Date Code>
1,2
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100ELT20N+
T0+
<Date Code>
1,2
AZM
MLP 16 (3x3)
AZ10/100ELT20L
T20
1,2
<Date Code>
MLP 16 (3x3)
Lead-Free
AZ10/100ELT20L+
AZM+
T20
<Date Code>
1,2
SOIC 8
AZ10ELT20D
AZM10
ELT20
1,2,3
SOIC 8
AZ100ELT20D
AZM100
ELT20
1,2,3
TSSOP 8
AZ100ELT20T
AZH
LT20
1,2,3
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
AZ100ELT20T+
AZH+
LT20
1,2,3
DIE
AZ10/100ELT20XP N/A
4
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week.
3 Date code “YWW” or “YYWW” on underside of part.
4 Waffle Pack.
The AZ10/100ELT20 is a CMOS/TTL to differential PECL translator. It operates with a single power supply of
+3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications. The extremely small
MLP 8 2x2 mm package makes it ideal for those applications where space, performance and low power are at a
premium.
When the D input is left floating, the Q output is forced HIGH, and the Q¯ output is forced LOW.
The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels
while the AZ100ELT20 is compatible with PECL 100K logic levels.
NOTE: Specifications in the PECL tables are valid when thermal equilibrium is established.
BLOCK DIAGRAM
Q
D
Q
1630 S. STAPLEY DR., SUITE 125 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com

1 page




AZ10ELT20 pdf
AZ10ELT20
AZ100ELT20
DIE PAD COORDINATES
AZ10/100ELT20 DIE:
ELT20 22
A
M
LK
B DIE SIZE: 950u X 940u
DIE THICKNESS: 14 mils
C BOND PAD: 85u X 85u
J
I
H
DG
EF
Note: Other die thicknesses available. Contact factory for further information.
The die backside may be left open or connected to GND.
PAD CENTER COORDINATES
NAME
A
B
C
D
E
F
G
H
I
J
K
L
M
NC = No connect, leave open.
PAD DESIGNATION
NC
NC
D
NC
VCC
VCC
Q
NC
NC
NC
10K
GND
X(Microns)
-342.5
-342.5
-342.5
-342.5
-33.5
126.5
312.5
312.5
312.5
312.5
302.5
142.5
-140.5
Y(Microns)
312.5
144.5
-87.0
-255.0
-312.5
-312.5
-248.5
-98.5
51.5
201.5
342.5
342.5
342.5
April 2005 * REV - 14
www.azmicrotek.com
5

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