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PDF 28F640L30 Data sheet ( Hoja de datos )

Número de pieza 28F640L30
Descripción (28FxxxL30) Wireless Memory
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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1.8 Volt Intel StrataFlash® Wireless
Memory with 3.0-Volt I/O (L30)
28F640L30, 28F128L30, 28F256L30
Datasheet
Product Features
High performance Read-While-Write/Erase
— 85 ns initial access
— 52MHz with zero wait state, 17 ns clock-to-data
output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 µs/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming @ 10 µs/byte (Typ)
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Multiple 16-Mbit partitions: 256Mb devices
— Four 16-KWord parameter blocks: top or
bottom configurations
— 64K-Word main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status register for partition and device status
Power
— 1.7 V - 2.0 V VCC operation
— I/O voltage: 2.2 V - 3.3 V
— Standby current: 30 µA (Typ)
— 4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
— Automatic Power Savings (APS) mode
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator (FDI) optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
Security
— OTP space:
— 64 unique device identifier bits
— 64 user-programmable OTP bits
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
Density and Packaging
— 64-, 128- and 256-Mbit density in VF BGA
packages
— 128/0, and 256/0 Density in Stacked-CSP
— 16-bit wide data bus
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O product is the latest generation of
Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high
performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multi-
level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background.
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O device is manufactured using Intel
0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale packaging.
.
Notice: This document contains information on products in the design phase of
development. The information here is subject to change without notice. Do not finalize
a design with this information.
Order Number: 251903-003
April 2003

1 page




28F640L30 pdf
28F640L30, 28F128L30, 28F256L30
12.0
AC Characteristics...................................................................................................55
12.1
12.2
12.3
12.4
12.5
12.6
AC Read Specifications (VCCQ = 2.2 V – 3.3 V) ................................................55
AC Write Specifications.......................................................................................60
Program and Erase Characteristics ....................................................................64
Reset Specifications............................................................................................64
AC Test Conditions .............................................................................................65
Capacitance ........................................................................................................66
Appendix A Write State Machine (WSM) ...........................................................................67
Appendix B Flowcharts ............................................................................................................74
Appendix C Common Flash Interface ................................................................................83
Appendix D Mechanical Information...................................................................................93
Appendix E Additional Information.....................................................................................97
Appendix F Ordering Information for VF BGA Package ............................................98
Appendix G Ordering Information for S-CSP Package ...............................................99
5

5 Page





28F640L30 arduino
28F640L30, 28F128L30, 28F256L30
2.3 Ballout Diagrams for Intel® Stacked Chip Scale Package
The 1.8 Volt Intel StrataFlash® wireless memory in Quad+ ballout device is available in an 88-ball
(80-active ball) Intel® Stacked Chip Scale Package for the 128-Mbit device and in an 88-ball (80-
active ball) Intel® Ultra-Thin Stacked Chip Scale Package for the 256-Mbit device. Figure 3 shows
the signal ballout. Refer to Section 5.0 for Mechanical Package Information.
Figure 3. 88-Ball (80-Active Ball) Stacked-CSP Package Ballout
123 4 567 8
A DU DU
DU DU
B
A4
A18
A19
V SS F1 -V CC F2-V CC
A2 1
A11
C
A5
R-LB#
A23
VSS
S -CS 2
CLK
A2 2
A12
D
F-V P P ,
A3
A17
A24 F-V PE N R-W E# P1 -CS #
A9
A13
E
A2
A7
A25 F-W P # ADV #
A20
A1 0
A15
F
A1
A6 R-UB# F-RS T# F-WE #
A8
A1 4
A16
G
A0
D8
D2
D10
D5
D13
WAIT F2-CE #
H
R-O E #
D0
D1
D3
D1 2
D14
D7 F2-O E#
J
S-CS 1# F1-O E #
D9
D11
D4
D6
D1 5
VCCQ
K
F1-CE# P 2-CS # F3 -CE# S-V CC P -VCC F2-V CC V CCQ P-Mode
L
VSS
V S S V CCQ F1-V CC V S S
VSS
VSS
VSS
M DU DU
DU DU
Legend:
T o p View - B a ll Sid e D o w n
S R A M /P S R A M sp e cific
G lo b a l
F la sh sp e cific
Datasheet
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