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PDF IDT71V2577SA Data sheet ( Hoja de datos )
| Número de pieza | IDT71V2577SA | |
| Descripción | (IDT71V2577S / IDT71V25779) Synchronous SRAMs | |
| Fabricantes | IDT | |
| Logotipo |  |
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128K x 36, 256K x 18
3.3V Synchronous SRAMs
2.5V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V2577S
IDT71V2579S
IDT71V2577SA
IDT71V2579SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 2.5V I/O
x Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
Pin Description Summary
A0-A17
Address Inputs
Description
The IDT71V2577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V2577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Input Synchronous
CE Chip Enable
Input Synchronous
CS0, CS1
Chip Selects
Input Synchronous
OE Output Enable
Input Asynchronous
GW Global Write Enable
Input Synchronous
BWE Byte Write Enable
Input Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV Burst Address Advance
Input Synchronous
ADSC
Address Status (Cache Controller)
Input Synchronous
ADSP
Address Status (Processor)
Input Synchronous
LBO Linear / Interleaved Burst Order
Input DC
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS Ground
Supply
N/A
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V2579.
© 2003 ntegrated Device Technology, Inc.
1
4877 tbl 01
JUNE 2003
DSC-4877/08
1 page  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
4877 drw 02a
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.452
5 Page 
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation
GW BWE BW1 BW2 BW3 BW4
Read
HHX X X X
Read
HL HHHH
Write all Bytes
LXXXXX
Write all Bytes
HL L L L L
Write Byte 1(3)
HL L HHH
Write Byte 2(3)
HL HL HH
Write Byte 3(3)
HL HHL H
Write Byte 4(3)
HL HHHL
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V2579.
3. Multiple bytes may be selected during the same cycle.
4877 tbl 12
Asynchronous Truth Table(1)
Operation(2)
OE
Read L
Read H
Write X
Deselected
X
Sleep Mode
X
ZZ
L
L
L
L
H
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
I/O Status
Data Out
High-Z
High-Z – Data In
High-Z
High-Z
Power
Active
Active
Active
Standby
Sleep
4877 tbl 13
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
A1 A0 A1 A0
First Address
000 1
Second Address
0 10 0
Third Address
10 11
Fourth Address(1)
1 110
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
A1 A0 A1 A0
First Address
000 1
Second Address
0 110
Third Address
10 11
Fourth Address(1)
1 10 0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 3
A1 A0
10
11
00
01
Sequence 3
A1 A0
10
11
00
01
Sequence 4
A1 A0
11
10
01
00
4877 tbl 14
Sequence 4
A1 A0
11
00
01
10
4877 tbl 15
6.1412
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IDT71V2577SA.PDF ] | |
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