PDF DS26102 Data sheet ( Hoja de datos )

Número de pieza	DS26102
Descripción	16-Port TDM-to-ATM PHY
Fabricantes	Maxim Integrated Products
Logotipo
Hay una vista previa y un enlace de descarga de DS26102 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! www.DataSheet4U.com www.maxim-ic.com GENERAL DESCRIPTION On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering (up to 4 cells), HEC generation and insertion, cell scrambling, and converts the data to a serial stream appropriate for interfacing to a T1/E1 framer or transceiver. On the receive side, the DS26102 receives a TDM stream from a T1/E1 framer or transceiver; searches for the cell alignment; verifies the HEC; provides cell filtering, descrambling, and cell buffering; and passes the cells to an ATM device through the UTOPIA II interface. Other low-level traffic management functions are selectable for the transmit and receive paths. The DS26102 can also be used in fractional T1/E1 applications. The DS26102 maps ATM cells to T1/E1 TDM frames as per the ATM Forum Specifications af-phy-0016.000 and af-phy-0064.000. In the receive direction, the cell delineation mechanism used for finding ATM cell boundary within T1/E1 frame is performed as per ITU I.432. The DS26102 provides a mapping solution for up to 16 T1/E1 TDM ports. The terms physical layer (PHY) and line side are used synonymously in this document and refer to the device interfacing with the line side of the DS26102. The terms ATM layer and system side are used synonymously and refer to the DS26102’s UTOPIA II interface. FUNCTIONAL DIAGRAM 16 TDM PORTS DS26102 UTOPIA II DS26102 16-Port TDM-to-ATM PHY FEATURES § Supports 16 T1/E1 TDM Ports § Supports Fractional T1/E1 § Compliant to ATM Forum Specifications for ATM Over T1 and E1 § Standard UTOPIA II Interface to the ATM Layer § Configurable UTOPIA Address Range § Configurable Tx FIFO Depth to 2, 3, or 4 Cells § Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction per ITU I.432 § Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition § HEC-Based Cell Delineation § Single-Bit HEC Error Correction in the Receive Direction § Receive HEC-Errored Cell Filtering § Receive Idle/Unassigned Cell Filtering § User-Definable Cell Filtering § 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor Interface § Internal Clock Generator Eliminates External High-Speed Clocks § Internal One-Second Timer § Detects/Reports Up to Eight External Status Signals with Interrupt Support § IEEE 1149.1 JTAG Boundary Scan Support § 17mm x 17mm, 256-Pin CSBGA Features continued on page 5. APPLICATIONS DSLAMS ATM Over T1/E1 Routers IMA ORDERING INFORMATION PART DS26102 TEMP RANGE -40°C to +85°C PIN-PACKAGE 256 CSBGA Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 64 REV: 021403 1 page 1. FEATURES § Supports 16 T1/E1 Ports § Supports Fractional T1/E1 and Arbitrary Bit Rates in Multiples of 64kbps (DS0/TS) Up to 2.048Mbps § Supports Clear E1 § Compliant to the ATM Forum Specifications for ATM Over T1 and E1 § Standard UTOPIA II Interface to the ATM Layer § Configurable UTOPIA Address Range § Generic 8-Bit Asynchronous Microprocessor Interface for Configuration and Status Indications Including Interrupt Capability § Physical Layer Interface Can Accept T1/E1 TDM Stream in the Form of Either (1) Clock, Data, and Frame-Overhead Indication or (2) Gapped Clock (Gapped at Overhead Positions in the Frame) and Data § Selectable Active Clock Edge for Interface with the T1/E1 Framer § Supports Diagnostic Loopback § Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction as per the ITU I.432 for the Cell-Based Physical Layer § Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition § Option of Using Either Idle or Unassigned Cells for Cell-Rate Decoupling in Transmit Direction DS26102 16-Port TDM-to-ATM PHY § 1-Byte Programmable Pattern for Payload of Cells Used for Cell-Rate Decoupling § Tx FIFO Depth Configurable to Either 2, 3, or 4 Cells § Transmit FIFO Depth Indication for 2-Cell Space Through External Pins § Optional Single-Bit HEC Error Insertion § HEC-Based Cell Delineation as per I.432 § Optional Single-Bit HEC Error Correction in the Receive Direction § Optional Filtering of HEC-Errored Cells Received § Optional Receive Idle/Unassigned Cell Filtering § Optional User-Defined Cell Filtering Based on Programmable Header Bits § Programmable Loss-Of-Cell Delineation (LCD) Integration and Interrupt § Interrupt for FIFO Overrun in Receive Direction § Saturating Counts for (1) Number of Error-Free Assigned Cells Received and Transmitted and (2) Number of Correctable and Uncorrectable HEC-Errored Cells Received § Selectable Internally Generated Clock (System Clock Divided by 8) in Diagnostic Loopback Mode § Integrated PLL Generates High-Frequency Clocks § IEEE 1149.1 JTAG Boundary Scan Support 2. APPLICABLE STANDARDS [1] ATM Forum “DS1 Physical Layer Specification,” af-phy-0016.000, September 1994 [2] ATM Forum “E1 Physical Layer Specification,” af-phy-0064.000, September 1996 [3] ATM Forum “UTOPIA Level 2 Specification,” Version 1.0, af-phy-0039.000, June 1995 [4] B-ISDN User-Network Interface—Physical Layer Specification—ITU-T Recommendation I.432—3/93 5 of 64 5 Page DS26102 16-Port TDM-to-ATM PHY PIN D6 B6 A5 A4 C4 T11 M12 G1 H4 H1 H3 D3 A2 C3 B3 A3 G4 G3 G2 H5 F2 F1 F4 F5 E2 E3 E1 E4 D2 D1 G5 F3 F8, F9, G8, G9, H6, H7, H10, H11, J6, J7, J10, J11, K8, K9, L8, L9 F6, F7, F10, F11, G6, G7, G10, G11, H8, H9, J8, J9, K6, K7, K10, K11, K14, K15, L6, L7, L10, L11 D13 NAME TFP3 TFP4 TFP5 TFP6 TFP7 TFP8 TFP9 UT_2CLAV0 UT_2CLAV1 UT_2CLAV2 UT_2CLAV3 UT_ADDR0 UT_ADDR1 UT_ADDR2 UT_ADDR3 UT_ADDR4 UT_CLAV0 UT_CLAV1 UT_CLAV2 UT_CLAV3 UT_CLK UT_DATA0 UT_DATA1 UT_DATA2 UT_DATA3 UT_DATA4 UT_DATA5 UT_DATA6 UT_DATA7 UT_ENB UT_PAR UT_SOC VDD VSS WR (R/W) Note 1: Address-latch enable for muxed bus. Note 2: Open-drain output. I/O FUNCTION I/O Tx Frame Pulse for Port 3 I/O Tx Frame Pulse for Port 4 I/O Tx Frame Pulse for Port 5 I/O Tx Frame Pulse for Port 6 I/O Tx Frame Pulse for Port 7 I/O Tx Frame Pulse for Port 8 I/O Tx Frame Pulse for Port 9 O Tx UTOPIA 2 Cells Available 0 O Tx UTOPIA 2 Cells Available 1 O Tx UTOPIA 2 Cells Available 2 O Tx UTOPIA 2 Cells Available 3 I Tx UTOPIA Address 0 (LSB) I Tx UTOPIA Address 1 I Tx UTOPIA Address 2 I Tx UTOPIA Address 3 I Tx UTOPIA Address 4 (MSB) O Tx UTOPIA Cell Available 0 O Tx UTOPIA Cell Available 1 O Tx UTOPIA Cell Available 2 O Tx UTOPIA Cell Available 3 I Tx UTOPIA Clock I Tx UTOPIA Data Bus 0 (LSB) I Tx UTOPIA Data Bus 1 I Tx UTOPIA Data Bus 2 I Tx UTOPIA Data Bus 3 I Tx UTOPIA Data Bus 4 I Tx UTOPIA Data Bus 5 I Tx UTOPIA Data Bus 6 I Tx UTOPIA Data Bus 7 (MSB) I Tx UTOPIA Enable (Active Low) I Tx UTOPIA Parity Bit I Tx UTOPIA Start of Cell — Positive Supply — Ground I Write Enable (Active Low) 11 of 64 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet DS26102.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
DS26101	8-Port TDM-to-ATM PHY	Maxim Integrated Products
DS26102	16-Port TDM-to-ATM PHY	Maxim Integrated Products

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar