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PDF DS26101 Data sheet ( Hoja de datos )
| Número de pieza | DS26101 | |
| Descripción | 8-Port TDM-to-ATM PHY | |
| Fabricantes | Maxim Integrated Products | |
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GENERAL DESCRIPTION
On the transmit side, the DS26101 receives ATM cells
from an ATM device through a UTOPIA II interface,
provides cell buffering (up to 4 cells), HEC generation
and insertion, cell scrambling, and converts the data
to a serial stream appropriate for interfacing to a
T1/E1 framer or transceiver. On the receive side, the
DS26101 receives a TDM stream from a T1/E1 framer
or transceiver; searches for the cell alignment; verifies
the HEC; provides cell filtering, descrambling, and cell
buffering; and passes the cells to an ATM device
through the UTOPIA II interface. Other low-level traffic
management functions are selectable for the transmit
and receive paths. The DS26101 can also be used in
fractional T1/E1 applications.
The DS26101 maps ATM cells to T1/E1 TDM frames
as specified in ATM Forum Specifications af-phy-
0016.000 and af-phy-0064.000. In the receive
direction, the cell delineation mechanism used for
finding ATM cell boundary within T1/E1 frame is
performed as per ITU I.432. The DS26101 provides a
mapping solution for up to 8 T1/E1 TDM ports. The
terms physical layer (PHY) and line side are used
synonymously in this document and refer to the
device interfacing with the line side of the DS26101.
The terms ATM layer and system side are used
synonymously and refer to the DS26101’s UTOPIA II
interface.
FUNCTIONAL DIAGRAM
8 TDM
PORTS
Dallas
Semiconductor
DS26101
UTOPIA II
DS26101
8-Port TDM-to-ATM PHY
FEATURES
§ Supports 8 T1/E1 TDM Ports
§ Supports Fractional T1/E1
§ Compliant to ATM Forum Specifications for ATM
Over T1 and E1
§ Standard UTOPIA II Interface to the ATM Layer
§ Configurable UTOPIA Address Range
§ Configurable Tx FIFO Depth to 2, 3, or 4 Cells
§ Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
per ITU I.432
§ Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
§ HEC-Based Cell Delineation
§ Single-Bit HEC Error Correction in the Receive
Direction
§ Receive HEC-Errored Cell Filtering
§ Receive Idle/Unassigned Cell Filtering
§ User-Definable Cell Filtering
§ 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor
Interface
§ Internal Clock Generator Eliminates External
High-Speed Clocks
§ Internal One-Second Timer
§ Detects/Reports Up to Eight External Status
Signals with Interrupt Support
§ IEEE 1149.1 JTAG Boundary Scan Support
§ 17mm x 17mm, 256-pin CSBGA
APPLICATIONS
DSLAMS
ATM Over T1/E1
Routers
IMA
ORDERING INFORMATION
PART
DS26101
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
256 CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 62
REV: 032503
1 page  
1. FEATURES
§ Supports 8 T1/E1 Ports
§ Supports Fractional T1/E1 and Arbitrary Bit
Rates in Multiples of 64kbps (DS0/TS) Up to
2.048Mbps
§ Supports Clear E1
§ Compliant to the ATM Forum Specifications for
ATM Over T1 and E1
§ Standard UTOPIA II Interface to the ATM Layer
§ Configurable UTOPIA Address Range
§ Generic 8-Bit Asynchronous Microprocessor
Interface for Configuration and Status Indications
Including Interrupt Capability
§ Physical-Layer Interface can Accept T1/E1 TDM
Stream in the Form of Either (1) Clock, Data, and
Frame-Overhead Indication or (2) Gapped Clock
(Gapped at Overhead Positions in the Frame)
and Data
§ Selectable Active Clock Edge for Interface with
the T1/E1 Framer
§ Supports Diagnostic Loopback
§ Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
as per the ITU I.432 for the Cell-Based Physical
Layer
§ Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
§ Option of Using Either Idle or Unassigned Cells
for Cell-Rate Decoupling in Transmit Direction
DS26101 8-Port TDM-to-ATM PHY
§ 1-Byte Programmable Pattern for Payload of
Cells Used for Cell-Rate Decoupling
§ Tx FIFO Depth Configurable to either 2, 3, or 4
Cells
§ Transmit FIFO Depth Indication for 2-Cell Space
Through External Pins
§ Optional Single-Bit HEC-Error Insertion
§ HEC-Based Cell Delineation as per I.432
§ Optional Single-Bit HEC Error Correction in the
Receive Direction
§ Optional Filtering of HEC-Errored Cells Received
§ Optional Receive Idle/Unassigned Cell Filtering
§ Optional User-Defined Cell Filtering Based on
Programmable Header Bits
§ Programmable Loss-of-Cell Delineation (LCD)
Integration and Interrupt
§ Interrupt for FIFO Overrun in Receive Direction
§ Saturating Counts for (1) Number of Error-Free
Assigned Cells Received and Transmitted and
(2) Number of Correctable and Uncorrectable
HEC-Errored Cells Received
§ Selectable Internally Generated Clock (System
Clock Divided by 8) in Diagnostic Loopback
Mode
§ Integrated PLL Generates High-Frequency
Clocks
§ IEEE 1149.1 JTAG Boundary Scan Support
2. LIST OF APPLICABLE STANDARDS
[1] ATM Forum “DS1 Physical Layer Specification,” af-phy-0016.000, September 1994
[2] ATM Forum “E1 Physical Layer Specification,” af-phy-0064.000, September 1996
[3] ATM Forum “UTOPIA Level 2 Specification,” Version 1.0, af-phy-0039.000, June 1995
[4] B-ISDN User-Network Interface—Physical Layer Specification—ITU-T Recommendation I.432—3/93
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5 Page 
6. SIGNAL DEFINITIONS
DS26101 8-Port TDM-to-ATM PHY
6.1 Line-Side Signals
Signal Name:
RCLK0–7
Signal Description:
Receive Line Clock (Ports 0 to 7)
Signal Type:
Input
The physical layer device uses the RCLK input to latch the RDATA and RFP signals. RDATA and RFP are sampled
by the receive section at either the positive edge or negative edge of RCLK, as controlled by the RAES (RCR2.2)
control bit. RCLK is gapped during nonactive and framing bit positions in gapped-clock mode (RPLIM = 1). RCLK
should be glitch-free.
Signal Name:
RDATA0–7
Signal Description:
Receive Line Data (Ports 0 to 7)
Signal Type:
Input
The RDATA input carries the receive bit stream. If the RCLK is gapped at framing bit positions, RDATA is then
sampled at every RCLK tick. If RCLK is not gapped and RFP is used to indicate framing bit positions, the RDATA
bits that are not associated with framing-overhead bits are sampled and cell delineated. In clear E1, RDATA is
sampled at every RCLK tick.
Signal Name:
RFP0–7
Signal Description:
Receive Frame Pulse (Ports 0 to 7)
Signal Type:
Input
This active-high signal indicates the framing-overhead bit positions corresponding to RDATA. For T1/E1, this aligns
with the first bit of the T1/E1 frame. For T1, RDATA coming at the RFP position is ignored. For E1, RFP is used to
identify TS0 (RFP position is bit 0 of TS0) and TS16 locations, and RDATA coming at these slots are ignored. In
clear E1, RFP is ignored. In frame-pulse mode, the RFP should come once every 125ms.
Signal Name:
TCLK0–7
Signal Description:
Transmit Line Clock (Ports 0 to 7)
Signal Type:
Input
The TCLK input is used by the DS26101’s transmit section to launch TDATA and TFP (when configured as an
output) at either positive edge or negative edge, as controlled by the TAES (TCR2.2) control bit.
Signal Name:
TDATA0–7
Signal Description:
Transmit Line Data (Ports 0 to 7)
Signal Type:
Output
The TDATA output carries the transmit bit stream. ATM layer data bits are not transmitted during framing/overhead
bit locations. TDATA is output at the TCLK configured active edge.
Signal Name:
TFP0–7
Signal Description:
Transmit Frame Pulse (Ports 0 to 7)
Signal Type:
Input/Output
This active-high signal can be set as an input or an output by using the TFSD (TCR2.0) control bit. TFP indicates
the frame-overhead bit positions corresponding to TDATA. For T1/E1, this signal aligns with the first bit of the
T1/E1 frame. For T1, TDATA coming at the TFP position does not contain valid data bit. For E1, TFP is used to
identify TS0 (TFP position is bit 0 of TS0) and TS16. TDATA does not contain valid data at these locations. After
RESET, the DS26101 is configured to use this signal as an input. In frame-pulse mode, the TFP should occur once
every 125ms.
11 of 62
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS26101.PDF ] | |
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